Mr. Mototsugu Okushima

Renesas Electronics, Japan

Talk Title:
Efficient CDM Protection Design for Cross Power Domain of Analog/RF block in Finfet Technology

Abstract:
Analog/RF circuit blocks that need noise isolation from digital block or each other are increasing more. To protect the vulnerable transistor in finfet technology, power clamp between cross domain is useful. However, increasing number of isolated blocks costs large area for the ESD clamps. To suppress the area increase, this presentation gives an efficient CDM protection design for cross-domain interface circuits especially using "internal cross clamp" as voltage divider between the internal power supply node of analog circuits and the digital GND node. The proposed protection circuit meets high CDM current request from large package IC with finFET technology while suppressing the area increase for analog/RF circuit blocks.

Dr. Teruo Suzuki

Socionext Inc

Talk Title:
Consideration based on ESD applied waveform in High-Speed IF using T-Coil

Abstract:
The T-Coil is one of the indispensable circuits in high-speed IF circuits and can reduce the effect of parasitic capacitance in ESD protection circuit. We fabricated a TEG equipped with ESD protection circuit, using the T-Coil driven by the state-of-the-art CMOS technology and investigated its performance. CDM failed at about 3.5A, VF-TLP failed at 2.2A, and the simulation reproduced those measurements. The effect of T-Coil mutual induced voltage is particularly pronounced in VF-TLP and is inconsistent with CDM. Since VF-TLP (TLP) is a tool for ESD design, ESD designers should consider this finding especially for leading-edge CMOS technology processes. There have been some reports of miscorrelation between TLP and ESD measurements, and the T-Coil is yet another case.

Dr. Dolphin Abessolo Bidzo

NXP Semiconductors, The Netherlands

Talk Title:
Electronic Design Automation (EDA) Layout Verification Methodology for Charged Device Model (CDM)

Abstract:
ESD Electronic Design Automation (EDA) verification tools have become instrumental to the design and verification flow of integrated circuits (IC’s). This trend has been mostly driven by the extraordinary development and increasing complexity of IC’s in the past few years. With the downscaling of the process technology nodes, CDM represents the main ESD threat for IC’s in assembly lines. Furthermore, increasingly demanding product performance with necessary ESD reliability requirements make it very challenging to achieve first-time-right silicon for both functional and ESD exigency. In that context, the use of ESD verification tools to de-risk IC designs before tape-out or for debugging purpose has become critical. ESD verification is not limited to circuit topology analysis. In order to improve its coverage, further geometrical, layout-based checks and simulations are required to verify the proper construction and implementation of ESD protection devices. Complementary to the topological ESD checks, these CDM layout simulations are meant to identify weak ESD paths, to perform a detailed analysis of back-end metallization and to spot victim devices (e.g. gate oxide of MOS devices) exceeding breakdown voltages under CDM like circumstances. The layout verification for CDM is performed at full chip level typically. In this presentation, the methodology of the state of the art CDM layout simulations tools is described, real life case studies are presented and the outlook towards future developments is discussed.

Dr. Matteo Buffolo

University of Padova - Department of Information Engineering, Italy

Talk Title:
Robustness of GaN-based LED against EOS events and ESDs

Abstract:
Over the last twenty years, the reliability of GaN-based visible LEDs has vastly improved, mostly due to optimizations in device structure and in the epitaxial growth, to a point where a useful lifetime of the solid-state source in excess of tens of thousands of hours can be achieved. For these mature devices, extrinsic factors, such as EOS and ESD events, represent a major lifetime-limiting factors during operation on the field. This talk investigates from a physical standpoint the impact of overstress events on GaN-based LEDs, and reports on the device-level mitigation strategies that can be adopted to improve LED robustness against such phenomena.

Ms. Yang Yanjing

ThermoFisher Sci/Singapore

Talk Title:
Failure Analysis workflow for Advanced Packing and Power Semiconductor Device

Abstract:
As semiconductor packaging evolves with technologies like 3D-IC, 2.5D, and wafer-level packaging, new reliability and performance challenges emerge, such as die-level defects, TSV formation issues, and bonding problems. Identifying these faults is crucial yet complex, requiring advanced techniques for rapid, precise, and accurate data. This talk will delve into the failure analysis workflow for advanced packaging and power semiconductor devices. It will cover process metrology, characterization challenges, and industry-leading workflows for assembly failure isolation and complete die analysis. Emphasizing techniques for high sample throughput, high resolution, and unmatched automation, the presentation will showcase how to accelerate failure analysis and reduce time-to-data, enhancing device performance, reliability, and yield.

Dr. Kranthi Nagothu

Texas Instruments

Talk Title:
On-chip protection Design Challenges for system level ESD (CDM)

Abstract:
In this presentation, unique failure mechanisms in high voltage Silicon Controlled Rectifiers (SCR) under IEC stress are discussed. In one case, the presence of a common mode choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in DeNMOS based SCR. In second, Air-Discharge IEC failure in Bi-Directional SCRs that are sensitive to IEC measurement conditions via the pulse rise time are investigated. 3D-TCAD simulations are used to develop the physical Insights of the failure and propose the device level engineering solutions to mitigate the IEC failures.