| 9:00 AM |
45 Mins |
Dr. Wolfgang Stadler (Gärtner & Stadler ESD Consulting, Germany) |
ESD Control for Chip Designers & Test Engineers (Keynote*) |
| 9:45 AM |
45 Mins |
Dr. Charvaka Duvvury (iT2 Technologies, USA) |
Five Decades of ESD Technology Development: Breakthrough Events and Milestones (Keynote) |
| 10:30 AM |
30 Mins |
Dr. Stefen Holland (Nexperia, Germany GmbH) |
System level ESD protection for high-speed data lines (Invited) |
| 11:00 AM |
20 Mins |
Break |
| 11:20 AM |
10 Mins |
Dr. Shin-ichi Iida (ULVAC-PHI) |
Advanced Surface and Interface Characterization for Semiconductor Devices Using XPS and SIMS (Platform Presentation*) |
| 11:30 AM |
30 Mins |
Prof. Carlo De Santi (University of Padova, Italy) |
TLP effects on normally-off p-GaN gate power HEMTs with Schottky gate (Invited) |
| 12:00 PM |
30 Mins |
Mr. Marcos Hernandez (Thermo Fisher Scientific) |
Charge Device Model (CDM) Electrostatic Discharge Test Using Low Impedance Contact CDM Method (LI-CCDM) (Contributed Talk) |
| 12:30 PM |
30 Mins |
Dr. Krzysztof Domanski (Intel, Germany) |
ESD codesign in leading-edge Ribbon-FET technologies (Invited*) |
| 1:00 PM |
90 Mins |
Networking Lunch |
| 2:30 PM |
30 Mins |
Dr. Karuna Nidhi (Tata Semiconductor Manufacturing Pvt. Ltd., Taiwan) |
ESD Design flow and Major concern for ICs (Invited) |
| 3:00 PM |
30 Mins |
Dr. Akram A Salman (Samsung Electronics, South Korea) |
State-of-the-art advances in ESD design and testing for Digital and Analog technologies (Invited) |
| 3:30 PM |
30 Mins |
Dr. Ping-Hsun, Su (Tata Semiconductor Manufacturing Pvt. Ltd., Taiwan) |
ESD Challenges from Process transfer into different Fabs (Invited) |
| 4:00 PM |
30 Mins |
Coffee Break |
| 4:30 PM |
15 Mins |
Prof. Sandip Lashkare (IIT Gandhinagar) |
Design Challenges and Considerations for Low Voltage System Level ESD Protection Devices (Contributed Talk) |
| 4:45 PM |
15 Mins |
Mr. Harshit Dhakad (Intel) |
Unraveling ESD HBM Failure on a Failsafe Interface in an Advanced FINFET Technology Node (Contributed Talk) |
| 5:00 PM |
15 Mins |
Mr. Surya Viswanathan (Infineon) |
CDM robustness improvement through decoupling capacitors in advanced CMOS technologies (Contributed Talk) |
| 5:15 PM |
15 Mins |
Mr. Vinod Kumar (Cadence Design Systems) |
ESD challenges of Designing high-speed interfaces in advanced nodes (Contributed Talk) |
| 5:30 PM |
15 Mins |
Mr. Gopikrishna Siddula (Western Digital) |
Designing ESD-Robust ASICs: A Practical Approach for Teams Without ESD Specialists (Contributed Talk) |
| 5:45 PM |
15 Mins |
Ms. Yogendri Vishwakarma (Rambus) |
Advanced EOS protection techniques (Contributed Talk) |
| 6:00 PM |
15 Mins |
Prof. Laxmeesha Somappa (IIT Bombay) |
On the ESD requirements and implementation challenges of Neural SoCs (Contributed Talk) |
| 6:15 PM |
15 Mins |
Ms. Roopa Hegde (Lam Research) |
Process window optimization for gate-all-around Electrostatic Discharge (ESD) diode (Platform Presentation) |
| 6:30 PM |
15 Mins |
Mr. Yaddanapudi Vamsi Krishna (Ansys) |
Simulation Solutions for Electrostatic Discharge (Platform Presentation) |
| 6:45 PM |
10 Mins |
Mr. Tristen Tan (Rohde & Schwarz) |
ESD Transient Pulse Verification Based on Oscilloscope (Platform Presentation) |
| 6:55 PM |
10 Mins |
Mr. Sadaf Arif Siddiqui (Keysight Technologies) |
Advancements in Semicon test validation with ESD perspective (Platform Presentation) |
| 7:05 PM |
10 Mins |
Concluding Remarks & Vote of Thanks & 7th InEW Announcement |
| 7:15 PM |
15 Mins |
Networking, Poster, Hi-tea, and See You @ 7th InEW |
