Poster Presentations
Design and Implementation of Bidirectional Ultra Low Capacitance Transient Voltage Suppressor Diode for System Level ESD Protection
G Yashan Kumar, Rathin Mahesh Ghivari, Ajinkya Sadavarte, Sandip Lashkare
(IIT Gandhinagar)
Abstract:
Electrostatic Discharge (ESD) protection safeguards microelectronic devices from fast, high-voltage/current transients that can cause catastrophic failure in integrated circuits. For high-frequency applications, ESD protection devices should withstand high ESD levels while maintaining ultra-low capacitance (ULC) to maintain signal integrity. Conventional ESD protection devices use Zener and PN diodes. These devices provide good protection but exhibit high capacitance (1–6 pF), which slows down the device response. Further, many applications would require bidirectional ESD protection, which adds additional limitations. In this work, a bidirectional ULC TVS diode is studied and analyzed for ESD failure levels, along with its capacitance performance, for high-speed applications. The ESD handling capacity is analyzed using Transmission Line Pulse (TLP) measurements, which provide an in-depth understanding of the TVS diode's physical behavior and failure mechanisms. A PCIe test case is used as a reference for demonstration with a fixed breakdown voltage. The ESD device has an area of 450 × 1 µm², is capable of handling an ESD current of 0.27 A/µm, and exhibits a total parasitic capacitance of 3.87 mF/µm. These ultra-low capacitance TVS diodes offer robust ESD protection and signal integrity, making them suitable for high-frequency applications. However, the same methodology can be applied to other high-speed applications such as USB, HDMI, Thunderbolt, CAN, and LIN, which operate at different voltages.
Mitigation of Gate Oxide Overstress during CDM Events using a Novel ESD Protection Structure in High-Speed RX Drivers
Saloni Rana
(Marvell India Private Limited, Bangalore)
Abstract:
Gate oxide reliability during Charged Device Model (CDM) events remains a critical challenge in deeply scaled high-speed interface circuits. Detailed ESD simulations identified excessive transient stress at an internal high-impedance decoder-driven PFET gate node caused by transient charge buildup and inadequate discharge paths during CDM events. To address this, a novel ESD mitigation structure was introduced to provide an effective transient clamp path without impacting normal operation. Simulation results demonstrate reduced peak gate stress, improving gate oxide reliability and overall ESD robustness in advanced high-speed RX drivers.
Improving Robustness of Dynamic ESD Clamps Against False Activation
Sanket Sonar
(STMicroelectronics)
Abstract:
Dynamic ESD clamps are essential for protecting integrated circuits, but their ramp rate sensitive behavior can lead to false triggering during normal operation of Fail-safe and non Fail-safe IOs. This work investigates robustness issues in both non-floating-rail and floating-rail clamp architectures, especially under fast functional supply ramps, glitches, and biased-rail disturbances. Different design approaches are presented to suppress unintended activation: a disable circuit referenced to an always-on or earlier-rising supply and a dual-condition trigger combining ramp-rate and voltage detection or use of diode to avoid false triggering. These techniques improve immunity to false turn-on while preserving ESD protection effectiveness. Trade-offs in area, tuning complexity and clamping voltage are discussed to guide application specific implementation choices.
Design & Implementation of Programmable Transmission Line Pulse Generation Technique
Amitabh Chatterjee
(Shiv Nadar University)
Abstract:
In our work we present designing a Transmission Line Pulser (TLP) that employs ultra-fast switching components to produce high-voltage, rectangular pulses. It delves into the fundamental physics of DC charging and discharging into a load, while providing practical mathematical formulas for calculating pulse width and amplitude. Design & Implemnetation explores various semiconductor options, such as avalanche transistors and GaN FETs, and emphasizes specific layout strategies with ability to control the pulse rise-time meeting HBM & CDM ESD standards. In addition to hardware implementation, the source details modeling for simulating electronic behavior and includes a thorough section on high-voltage safety protocols. Ultimately, these guidelines offer a comprehensive framework for engineering precision pulse generators used in ESD device testing and characterization.
3D PERC Verification in Advanced Packaging
Prashant
(Marvell Semiconductor India)
Abstract:
The increasing adoption of advanced semiconductor technologies and heterogeneous integration has led to the widespread use of multi-die packaging architectures. Ensuring ESD reliability and correct connectivity across such complex systems is a critical challenge. 3D Physical Electrical Rule Checking (3D PERC) provides a comprehensive framework for verifying electrical behavior, connectivity, and reliability across stacked designs consisting of multiple dies, interposers, and substrates. In this work, a methodology for 3D PERC-based system-level verification is presented, focusing on key aspects such as point-to-point (P2P) connectivity checks, topology validation, and resistance-based path verification. The approach enables accurate validation of signal paths and ensures correct electrical behavior across multiple layers of integration. Additionally, ESD-related verification, including discharge path validation and protection network analysis, is incorporated to ensure robust design reliability. The study also highlights challenges associated with 3D PERC verification, including complex multi-layer connectivity, large-scale power/ground networks, and debugging of topology violations. Techniques such as 3D-aware rule configuration, optimized rule implementation, and efficient debug methodologies are applied to improve verification accuracy and runtime efficiency. The proposed approach enables early detection of connectivity and reliability issues and provides a scalable and reusable verification solution for advanced multi-die and packaging technologies. This contributes to improved design robustness and reduced turnaround time in modern semiconductor design flows.
TCAD Study of a floating-p SCR-LDMOS Device
Giacomo Drudi
(University of Bologna)
Abstract:
A new SCR-LDMOS device is investigated through 2D and 3D TCAD simulations to obtain maximum holding voltage, minimum area and high ESD robustness. The effect of the additional floating-p region is studied analyzing the carrier and electric field distribution in the device with simulations. Reduced overvoltage and improved turn-on time are observed in the very-fast pulsed regime with respect to the device without floating-p. Tunability of holding voltage with drift length is shown. 3D effects are studied showing improved ruggedness to premature failure during snapback by mitigating current filamentation.
Why Schottky Contact in LDMOS Protects It From Filament Driven Catastrophic ESD Failure?
Shravya N Raj
(Indian Institute of Science)
Abstract:
In this work, well-calibrated electrothermal 3D TCAD simulations are used to investigate the behavior of Schottky drain LDMOS devices under ESD stress. The study examines ESD robustness for different Schottky drain metal work functions, with particular emphasis on current filament formation and evolution. The impact of drain-side Schottky barrier engineering is analyzed in detail to identify the appropriate metal silicide for achieving enhanced ESD protection. Transient ESD simulations reveal how variations in barrier height influence carrier injection, current spreading, and localized self-heating, which collectively govern filament stability and failure onset. The results provide physical insight into filament-driven catastrophic failure mechanisms and demonstrate that optimized Schottky drain design can effectively suppress current localization and improve ESD robustness.
Area Efficient Substrate Triggered SCR Based Local ESD Clamp Concepts with Tunable Trigger Voltage
Mitesh Goyal
(Indian Institute of Science)
Abstract:
An area-efficient substrate-triggered silicon-controlled rectifier (EPDSCR) device is presented for electrostatic discharge (ESD) protection in high-speed I/O applications. The device employs a co-engineered SCR structure and trigger circuit for enabling IO-VSS and IO-VDD local clamps, with reduced and tunable trigger voltage while maintaining low parasitic capacitance. By optimizing the substrate triggering mechanism and SCR conduction path, the proposed design achieves higher ESD robustness per unit area, lower on-resistance, and improved current handling capability compared to state-of-the-art SCR-based protection schemes. The reduced parasitic capacitance makes the device suitable for high-speed interfaces. The proposed concept is implemented and validated using multiple test chips fabricated in a 28-nm bulk CMOS process. Measurement results from TLP, vf-TLP, and DC characterization confirm enhanced IT2, reduced VT1, and improved ESD performance. The proposed EPDSCR meets the ESD requirements of modern I/O interfaces and provides robust protection across HBM and CDM stress conditions.
Physics Based Modeling of Space Charge Modulation Snapback in HV LDMOS Devices
Harihar Nath
(Indian Institute of Science)
Abstract:
A physics-based analytical model is developed for capturing the phenomenon of space charge modulation in the intrinsic NPN of the LDMOS device for a 100 ns TLP stress. Reverse-biased base–collector avalanche, current partitioning through the emitter diode and base resistance, and space charge modulation by injected electrons are coupled self-consistently to reproduce the snapback phenomenon and to form the basis for current filament formation. Model validation was also done by varying the n-well region's doping.
Unification of Filament Dynamics in LDMOS Devices across Voltage Classes
Shreenidhaa K K
(Indian Institute of Science)
Abstract:
Laterally-Diffused MOS (LDMOS) transistors are highly susceptible to electrostatic discharge (ESD) stress, with device failure primarily attributed to catastrophic filament formation leading to thermal runaway. Previous studies have examined the underlying filament formation and failure mechanisms independently for different voltage classes. Though the underlying physics is the same, there are ambiguities related to the slight differences in the filament dynamics with respect to different voltage classes. In this work, a unified framework is proposed to correlate and generalize the filament behaviour of LDMOS devices across multiple voltage classes. The analysis is carried out on devices with systematic doping variations within the drift region, enabling a comprehensive understanding of the failure dynamics as a function of voltage class.
Junction Engineered FinFET SCR for Ultimate Tunability of Trigger and Holding Voltage
Mayank Yadav
(Indian Institute of Science)
Abstract:
Proposed a junction-engineered FinSCR architecture for on-chip ESD protection with tunable holding and trigger voltages. Introduced deep implants and additional p–n/n–p junctions beneath fins to control parasitic PNP/NPN transistor behaviour. Achieved flexible ESD performance optimisation while maintaining high failure current capability through junction engineering and fin-count adjustment.
Ultra-fast TLP characterization of gate-all[1]around (GAA) ESD diodes for low-capacitance optimized I/Os
Anish K Kumar, Krzysztof Domanski, Raj S Dua, Reshma R Menon, Umair Ishfaq, Salukazi Shamutete, Florian Klotz, Harshit Dhakad and Anand Sharma
(Intel)
Abstract:
This paper presents the characterization and modeling of diodes fabricated using bulk and gate-all-around (GAA) technologies, highlighting the enhanced electrostatic discharge (ESD) robustness observed in the GAA FINFET node. Ultra-fast Transmission Line Pulse (uf-TLP) measurements with rise times of 40ps, and very-fast TLP (vf-TLP) measurements with rise times of 100ps were conducted, targeting both diode structures and gate oxide (GOX) victims. Diodes using non[1]planar FINs with bulk node exhibited slower response and higher forward recovery (FR) overshoot, whereas GAA diodes demonstrated faster switching behavior without FR overshoot. GOX structures in the bulk node failed prematurely due to FR-induced stress, in contrast to the more robust performance observed with GAA diodes. The overshoot-free switching of ESD diodes processed in GAA-FINFET Intel technology allows for improvement of several key performance indicators (KPI) in the High Speed (HS) interfaces, as shown on the example of DDR
Ghost Failures or Real Threats? Unmasking the Role of Inadvertent Device Charging in CDM Testing
Harshit Dhakad, Pavel Zisman, Chandrasekhar Korada, Anand Sharma
(Intel)
Abstract:
CDM (Charged Device Model) testing is the industry-standard method for qualifying integrated circuits against electrostatic discharge events that occur during automated handling and assembly. However, a less-discussed but practically significant problem exists — devices that arrive at the test setup carrying a residual electrostatic charge from prior handling, storage, or measurement steps or triboelectric charging of DUT within CDM tester. This inadvertent pre-test charging superimposes an additional current/voltage stress on top of the intended CDM pulse, pushing sensitive pins beyond their actual failure threshold and generating failures that would not occur under clean test conditions. This poster investigates the mechanism by which pre-existing device charge contributes to false failures, with particular focus on high-performance pins such as RF inputs, high-speed I/O, and analog signal ports — pins that are inherently more vulnerable due to thin gate oxides, tight ESD design windows, and low parasitic capacitance. Through a combination of controlled experiments, and correlation with failure signatures, we demonstrate that a meaningful fraction of observed CDM failures on these pins can be attributed to pre-test charging artifacts rather than genuine ESD weakness. The findings have direct implications for how CDM test results are interpreted, how test environments should be controlled, and how ESD design margins are set for sensitive pins. Practical recommendation for eliminating pre-test charging effects is discussed, with the goal of improving the reliability and repeatability of CDM qualification in production and characterization environments.