Poster Presentations
Custom ESD Protection for 10 V - Compliant Neural Stimulators in 65nm CMOS Technology.
Naef Ahmad, Tanay Das, Navin Maheshwari, Sandip Lashkare, Laxmeesha Somappa
(IIT Bombay, IIT Gandhinagar)
Abstract:
Implantable neurostimulators use internally generated high-voltages (up to 10V) to suppress seizures using a pair of electrodes. For such applications, traditional foundry provided ESD protection is inadequate due to such custom voltage requirements. Here, a pair of diodes is proposed as a custom ESD protection verified using schematic simulations (TSMC 65nm) with an HBM model. The diode structure's 2D layout is simulated in TCAD for TLP measurements to identify local temperature hotspots by current crowding and failure currents. Finally, multiple diode fingers are then implemented to distribute ESD current uniformly, reducing footprint and dynamic resistance, meeting the custom voltage requirement.
ESD Solution for Die-to-Die I/Os.
Bhawana Adhikari
(Synopsys)
Abstract:
Explore the future of semiconductor packaging with our insights into 2.5D and 3D technologies, featuring advanced Interposer and Silicon Interconnect solutions. While conventional IOs are familiar with ESD risk and solution, the emerging D2D IOs require a fresh outlook to meet IP ESD requirements with optimum area and performance impact. This poster will include detailed insight of our current offer in D2D IO and ESD solution implementation and will share how ESD solutions are made compatible with standard cell logic for seamless implementation of thousands of IOs with required ESD protection in digital flow.
Cross-Domain menace in an IO Cluster.
Siddharth Singh
(Synopsys)
Abstract:
The modern chips are moving to a single ground throughout the chip. Does it mean that the long-standing perilous event of cross-domain ESD has been solved? The cross-domain interface circuits can easily be damaged during cross-domain ESD events. Due to CDM charges distributed throughout the entire chip, charges need an effective cross-domain ESD path to discharge during an CDM event. In this study we analysed various cross-domain solutions which have been followed traditionally and recommended by the foundries. We analysed the significance of having an Anti-parallel diode between to separate ground domains alongside the impact of routing resistance of these diodes. Additionally, how having a dedicated cross-domain clamp mitigates the risk significantly. Lastly, we will discuss how having a single ground throughout the chip helps during ESD event. But does it mean we can overlook the cross-domain issue if we have single ground? The answer is NO. We will be discussing it with an intriguing cross-domain failure that we tackled on our Si testchip.
Adaptive ESD Protection Circuits: A Dynamic Approach to Enhancing Chip Reliability.
Abishekkumar A
(Anna University)
Abstract:
Electrostatic Discharge (ESD) is a major challenge in integrated circuit (IC) design and manufacturing. Traditional ESD protection methods lack flexibility for varying threats. This paper introduces Adaptive ESD Protection Circuits, which adjust protection mechanisms in real-time based on detected ESD events. Using smart sensing technologies and advanced algorithms, these circuits optimize protection while minimizing impact on normal operation. We discuss design principles, implementation challenges, and benefits over conventional methods. Case studies highlight significant improvements in ESD resilience and reliability, demonstrating the potential of adaptive ESD protection for future semiconductor designs.
Embedded Passives in Advanced Packaging: Enhancing ESD Protection and Circuit Performance
Prathipa L
(Anna University)
Abstract:
As the demand for miniaturized, high-performance electronics grows, advanced packaging techniques have become crucial. This paper explores the use of embedded passives, such as resistors, capacitors, and inductors, integrated within the chip package. This approach reduces parasitic elements, shortens signal paths, and enhances electrical performance and ESD protection. We highlight the design, fabrication processes, and benefits over traditional components, supported by simulations and experimental results. Case studies demonstrate improved ESD resilience and system reliability. Challenges and future directions in adopting embedded passives are discussed, emphasizing their potential to meet the stringent demands of modern electronics.
Charged Device Model Testing for the future.
Thomas Meuse
(Thermo Fisher Scientific)
Abstract:
More ESD related failures are occurring during manufacturing process, so testing devices to events such as those emulated by the Charge Device Model (CDM) test is becoming more important! The field-induced CDM method in ANSI/ESDSA/JEDEC JS-002 is widely used, however there are issues with this method, due to the air discharge created when initiating the discharge. One issue is the variation of the pulse amplitude, which becomes even more variable as the pre-charge voltage decreases. A contact method, referred to as low-impedance contact CDM (LI-CCDM) eliminates the air discharge and thereby improves repeatably and reproducibility. This method will be reviewed.
Interplay of Surface Passivation and Electric Field in Determining ESD Behaviour of p-GaN Gated AlGaN/GaN HEMTs.
Rasik Rashid Malik, Avinas N Shaji, Jayshree, Zubear Khan, Madhura, M. A. Munshi, Rajarshi R. Chaudhuri, Vipin Joshi, and Mayank Shrivastava
(Indian Institute of Science)
Abstract:
Electrostatic Discharge (ESD) is a major challenge in integrated circuit (IC) design and manufacturing. Traditional ESD protection methods lack flexibility for varying threats. This paper introduces Adaptive ESD Protection Circuits, which adjust protection mechanisms in real-time based on detected ESD events. Using smart sensing technologies and advanced algorithms, these circuits optimize protection while minimizing impact on normal operation. We discuss design principles, implementation challenges, and benefits over conventional methods. Case studies highlight significant improvements in ESD resilience and reliability, demonstrating the potential of adaptive ESD protection for future semiconductor designs.
Multifinger Turn-On Instability in Drain Extended Vertically Stacked Nanosheet FETs Under ESD Stress Conditions.
Jatin, M. Monishmurali and M. Shrivastava
(Indian Institute of Science & Currently with Analog Devices)
Abstract:
A multifinger drain extended (DE) nanosheet FET has been studied for its multifinger turn-on uniformity under electrostatic discharge (ESD) stress conditions using 3-D TCAD simulations. Current and temperature instabilities were seen in the multifinger devices under high current transmission line pulsing (TLP) stress. These instabilities, which may result in premature device failure, were found to be attributed to nonuniform finger turn-on. The physics of nonuniform turn-on in multifinger devices has been probed and on the basis of the observations drawn from the physical insights developed, novel extension fin engineering guidelines have been proposed to mitigate the nonuniform finger turn-on.
Origami method in ESD Packaging.
Ganesh T N Bhushan
(JAIN University)
Abstract:
The proposal of including origami in sustainable packaging is a surplus note on technological advancement. Specially from SIT, Japan, wherein a decade long emphasis of utilitarian amalgam of origami in minuting the space and enhancing packing efficiency is subjected to industrial mechanisms and machinery, But concerned to that of Electro-Static Devices, the tryst of adaption and implement could make a greater move for revolutionary remarks on ESD packaging. Currently, project proposals on implementing suitable paradigm methods of simulation and algorithm on MoC, design patterns and pain-points are focused under laboratory and working conditions of ESDs & piezo-static instrumentation, concerning to eradicate hazards and cautions.
Load-line Dependent Current Filament Dynamics in Nanoscale SCR Devices.
Mitesh Goyal, Mukesh Chaturvedi, Raju Kumar, Mahesh Vaidya, Mayank Shrivastava
(Indian Institute of Science & Samsung Semiconductor India Research)
Abstract:
In this work physics of experimentally observed abnormal behavior in STI bounded Silicon-Controlled-Rectifier (SCR) structures is investigated and explained using basic principles and 3D electrothermal TCAD simulations. The SCR device is found to show pulse to pulse instability in the negative resistance (snapback) region during the 100ns pulse width TLP measurement. The instabilities were independent of SCR geometrical design variations but were dependent on the load line conditions used in the TLP measurement. The physical insights and device physics has been explored using well calibrated 3D process and device TCAD.
Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR.
Mitesh Goyal, Mukesh Chaturvedi, Raju Kumar, Mahesh Vaidya, Mayank Shrivastava
(Indian Institute of Science & Samsung Semiconductor India Research)
Abstract:
In this work co-optimization of silicon-controlled rectifier (SCR) ESD characteristics with its low voltage trigger circuit is presented. Resistance and Capacitance (RC) controlled thick gate NMOS and PMOS based circuits have been explored and compared. The design approach is discussed and presented for low trigger SCR for two different trigger circuits. In the process we find that some of the trigger circuits previously reported in literature do not work as desired until co-optimized device engineering techniques are used. The circuit insights are explored using well calibrated electrothermal 3D process and device TCAD mixed mode simulations.
Current Scalability Issues in Multi-Bank 5V PMOS ESD structures: Root cause and Design Guideline.
Kranthi Nagothu, Yang Xiu, Yang Xiao, Rajkumar Sankaralingam
(Texas Instruments)
Abstract:
In this work, a unique Human Body Model (HBM) failure is presented in 5V-PMOS multi-finger structures. The failure is sensitive to the multi-bank layout, generally used to achieve higher holding voltage. Missing Transmission Line Pulse (TLP) failure current (It2) scalability is detected with pulse width, in multi-bank structures and a correlation is established with lower HBM failure. A detailed 3D-TCAD analysis approach is used to understand the PMOS turn-on in the singlebank and multi-bank structures, in turn, the It2 scalability for longer pulse width. The obtained insights are used to provide design guidelines for developing robust PMOS devices.
Understanding Temperature Dependence of ESD Breakdown in AlGaN/GaN HEMTs.
Mohammad Ateeb Munshi, Mehak Ashraf Mir, Vipin Joshi, Rajarshi Roy Chaudhuri, Zubear Khan, Mayank Shrivastava
(Indian Institute of Science)
Abstract:
In this work, we report the role of temperature on the ESD reliability of AlGaN/GaN HEMTs emulating system-level scenario. We compared two stacks with different buffer carbon doping concentration, LC (low carbon doping) and HC (high carbon doping). The failure voltage (Vbd) was seen to decrease with increasing temperature in LC, while Vbd remained independent of the temperature for HC. The modulation of electric field due to the temperature is seen to govern the ESD behavior of the LC. Inverse piezoeletric effect governs the breakdown in LC, while, as in HC, hot holes due to avalanche and hole emission in the high carbon doped buffer determine the breakdown behavior. This study shows the need of an optimum buffer to ensure the ESD robustness of AlGaN/GaN HEMTs with temperature.
Impact of a Deep Junction Coupled with a Short Channel Length on the ESD Robustness of a Grounded Gate NMOS Clamp.
Casey Hopper, Antonio Gallerano, Raj Sankaralingam
(Advanced Technology Development, Texas Instruments Inc.)
Abstract:
Several physical insights into the multi-finger turn-on in deep junction GGNMOS devices and its implication on eventual failure current is presented with detailed experiments. The impact of junction depth to channel length ratio is found to be a key design factor in obtaining ESD robustness.
Engineering Custom TLP Characteristic Using a SCR-Diode Series ESD Protection Concept.
Harsha B Variar, Satendra Kumar Gautam, Ashita Kumar, Amogh K M, Juan Luo, Ning Shi, David Marreiro, Shekar Mallikarjunaswamy and Mayank Shrivastava
(Indian Institute of Science and Alpha & Omega Semiconductor)
Abstract:
This work demonstrates an SCR-Diode series ESD Protection concept, which can be engineered to provide a custom TLP I-V characteristic. SCRs and diodes with dimensional variations have been used in different combinations and width ratios, which results in a range of TLP I-V characteristics. This protection circuit comes with several advantages as adaptability for various ESD protection windows, the benefits of using SCR as a protection device and the ease of designing the circuit. Along with TCAD studies, experimental data demonstrates that N-well and P-well doping of SCR can be used to further tune the Vhold and Ron of the protection circuit.
3D Approaches to Engineer Holding Voltage of SCR.
Suruchi Sharma, Satendra Kumar Gautam, Harsha B Variar, Juan Luo, Ning Shi, David Marreiro, Shekar Mallikarjunaswamy, Mayank Shrivastava
(Indian Institute of Science and Alpha & Omega Semiconductor)
Abstract:
Novel Silicon-Controlled-Rectifier (SCR) structures are experimentally demonstrated with the cathode and anode region engineering in the width (3D) plane. The engineering approach uses unique placements of P+ and N+ pockets/strips, instead of uniform anode/cathode implants. Experimental results show tunable holding voltages (3V - 10V) with high ESD failure current (It2) by using layout parameters related to the placement of these pockets/strips. The same has been demonstrated for over a dozen process lots. The physical insights and engineering guidelines into the holding voltage tuning has been explored using 3D process and device TCAD.
High-Performance LDMOS-SCR with Improved ESD Robustness.
Monishmurali M
(Texas Instruments)
Abstract:
Conventional LDMOS-SCR devices were improved to enhance their DC performance without flipping the anode side contacts. This was achieved by studying the PNP, NPN, and SCR triggers under DC operational conditions. NPN engineering was also investigated using TCAD to prevent failure during normal DC operation while maintaining the PNP action. A 72% increase in the maximum drive current was achieved on silicon by degrading the NPN alone and retaining the PNP action. Finally, the RF performance of all the variant of LDMOS devices are presented.
Effect of Source & Drain Side Abutting on the Low Current Filamentation in LDMOS-SCR Devices.
Monishmurali M, Kranthi Nagothu, Gianluca Boselli, Mayank Shrivastava
(Texas Instruments)
Abstract:
The concept of abutting source/body and drain/anode junctions is studied in detail in a high voltage LDMOS-SCR with 2D and 3D TCAD simulations. The SCR turn-on and low current filament formation are strongly influenced by the isolation at the anode and cathode side in the LDMOS-SCR. While the anode side isolation impacts the filament-induced failures at low currents, the cathode side isolation has a minor impact. Physical insights are given on the SCR turn-on degradation with abutting and its influence on the filament formation and spreading. The obtained understanding helps to build an ESD robust, self-protected LDMOS-SCRs.
TI’s Discrete Protection Diodes Portfolio with Ultra-Low Capacitance.
Kartikey Thakar
(Texas Instruments)
Abstract:
Did you know Texas Instruments has dedicated process technology for their discrete protection diodes? This is designed and optimized to achieve top-of-the-class ESD protection while achieving one of the lowest capacitance values for the same class of devices. TI protection diodes are designed to achieve suitable low cap required for slow data rate (a few Kb) to very high-speed data lines (USB2/3 HDMI1/2). In this talk, we discuss a range of external ESD protection solutions offered by TI for both Commercial/Industrial and Automotive applications, suitable for power as well as data lines.
Physics of ESD reliability in amorphous silicon based TFTs.
Rajat Sinha, Prasenjit Bhattacharya, Icko Eric Timothy Iben, Sanjiv Sambandan, Mayank Shrivastava
(Micron Technology India, Indian Institute of Science)
Abstract:
This work presents the physical behavior of non crystalline silicon based TFTs including dielectric breakdown and thermal failure under ESD Conditions. It also presents a unique phase transition behavior and explores device degradation under ESD Conditions.
Increased ESD robustness of non crystalline silicon based TFTs using novel architectures.
Rajat Sinha, Sanjiv Sambandan, Mayank Shrivastava
(Micron Technology India, Indian Institute of Science)
Abstract:
This works explores various device architectures that can be used to improve the ESD robustness of non crystalline materials based TFTs. These architectures are shown to have low real estate penalities and need not require additional masks steps.
ESD design methodology for GPIO design.
Dzung Tran, Saleh Omar, Vaibhav Katkar, Prashanth Singh, Mridula Pai, Thiru Ranganathan
(GlobalFoundries)
Abstract:
Soc Implementations demand robust design flow practices GPIP design. This paper describes an ESD design methodology for GPIO design.
BEOL Optimization of ESD devices for RF application
Sitansusekhar Roymohapatra
(GlobalFoundries)
Abstract:
Radio frequency (RF) electrostatic discharge (ESD) protection design is emerging as a new challenge to RF integrated circuits (IC) design. Designers are looking towards RFIC-ESD co-design to provide ESD protection devices with minimum possible capacitance. But in advanced node ESD protection devices, the capacitance offered by back-end-of-line (BEOL) is comparable to the front-end-of-line (FEOL) capacitance. The BEOL capacitance optimization is the need of the hour to offer robust HBM and CDM protection without degrading the RFIC performances. This poster reviews different designs for BEOL optimization of ESD protection devices.
ESD protected Isolation cell with low Leakage and complaint to power-aware verification
Pramod Gayakwad, Mukesh Kumar, Jeethu Benny, Gagan Kansal (NXP Semiconductors)
(NXP Semiconductors)
Abstract:
To reduce power consumption in chips, designs are partitioned into multiple power-domains, requiring additional circuits, such as Level Shifter, Always-ON and ISOlation cells. Signals crossing power domains need CDM ESD protection circuit and ISO/LS cells. Chip failures occurred when the ESD and ISO circuit connections were incorrectly connected and, in another situation, ESD circuit had an inaccurate timing model issue during System on Chip timing analysis. To resolve these problems, a resilient ESD+ISO macro cell was developed, which is power-aware for SoC design UPF implementation and verification needs, while having low leakage and accurate timing model.
