Anamika Chowdhury

Lam Research.

Talk Title:
Low Pressure Reactor Design to Avoid Unwanted Electrostatic Discharge

Abstract:
Arcing, which is one form of Electrostatic discharge, is a common phenomenon in plasma equipment, especially between components which have high potential difference or charge density. While arcing has many industrial applications including welding and combustion processes, unwanted arcing happening at and above the electrical breakdown voltages can result in equipment damage and yield loss.

Initial efforts focused on experimentally recording breakdown voltages under applied RF fields for a range of gases and electrode geometries [1-3]. Kihara [4] gave a kinetic treatment of processes occurring in RF electrical discharges in gases and obtained a condition for gas breakdown, which was further validated by Lisovskiy and Yegorenkov [5]. Recent research has focused on using Particle-In-Cell (PIC) simulations to improve agreement between theoretical and experimentally recorded Paschen curves [6-7]. In this talk, we will highlight the past scientific developments in calculation of breakdown voltage. Using a simplified plasma reactor geometry as an example, we demonstrate how reactor design is modified to eliminate arcing risk.

References

1. Gill E W B and Donaldson R H 1931 Phil. Mag. 12 719
2. Thomson J 1937 Phil. Mag. 23 1
3. Chenot M 1948 Ann. Phys., Paris 3 277
4. Kihara T 1952 Rev. Mod. Phys. 24 45
5. Lisovskiy V A and Yegorenkov V D 1994 Tech. Phys. Lett. 20 920
6. Wu H 2021 Plasma Sources Sci. Technol. 30 065029
7. Puač M 2018 Plasma Sources Sci. Technol. 27 075013

Mr. Anurag Mittal

Synopsys

Talk Title:
I/O ESD implementation for 2.5D/3D Applications

Abstract:
Multi-Die implementations require thousands of short communication I/O channels to drive and receive data. The channel is formed over an interposer, between dices that are in close proximity. It creates an imperative need for a fast and reliable integration of the Die 2 Die interface IOs in the 2.5 D/ 3 D design flow. Conventionally I/Os and ESD cells are Analog macros and need manual cluster-based placement in SoC design flow. We shall discuss in our presentation how our simplified offer caters to all these design challenges. Moreover, conventional CDM architectures may not be suitable for D2D implementations due to large area, cap and leakage constraints. We evaluate few conventional versus novel CDM architectures to meet high density multi-die I/O ESD implementations.

Mrs. Chinmayee Panigrahi

NXP Semiconductors

Talk Title:
Challenges in ESD protection for High Speed CML transmitter having thin oxide devices and their solution

Abstract:
ESD protection of High-Speed PADs is very challenging as ESD elements add capacitance to PAD which limits the max frequency of operation. This talk presents the challenges in ESD protection of CML transmitter for 5.5GHz Clock and 5.5 Gbps data in 0.9V Signaling, done in CLN28HPCP technology using thin oxide (GO1) devices. Ensuring sufficient ESD robustness for GO1 devices is difficult as protection circuit shall shunt the ESD current and keep the voltage drop below the failure voltage of GO1 devices. Conventional ESD strategy of direct ESD protection between differential PADs limits the bandwidth. An innovative ESD solution is used for achieving 5.5GHz frequency and at the same time achieving the ESD robustness.

Dr. Dattatreya Prabhu Rachakonda

GlobalFoundries

Talk Title:
Learnings from Switch Self-Protection : from models to hardware

Abstract:
The Switch is an integral component of any communication front end module. The configurations like Single Pole Double Throw (SPDT) employ a series-shunt combination of Mosfets (SwitchFETs). Being large devices (say >1mm in width) the devices are expected to self-protect from possible ESD events. This talk will aim to decipher the physics behind the ESD performance of the silicided SwitchFETs both at the device level as well as in the switch-stack configuration. Efforts to ascertain and replicate the observed failure current trends using TCAD and capture the geometric and bias dependence in a compact model will be highlighted. As a next step the performance of the compact model in predicting the transient behavior of the switch-stack vs. hardware will also be outlined.

Mr. Harshit Dhakad

Intel Technologies India Pvt

Talk Title:
Tracing and debugging of ESD failures in a module assembly line

Abstract:
His current work focusses on development of RF & high speed interface ESD protection concepts & ESD verification methodology for complex SoC’s ESD Testing Tracing and Debugging of ESD Failures in a Module Assembly Line A functional failure of a connectivity module is investigated and traced down to transistor level in the CMOS IC. The presentation discusses failure analysis, layout inspection, ESD simulations, ESD test experiments to validate and understand the root cause and process assessment in the assembly line. The analysis identified a charged board event as the issue.

Gopikrishna Siddula

Western Digital

Talk Title:
Enhancing Reliability in High speed and High-Density Storage: Practical Strategies for Mitigating Electrostatic Discharge (ESD)

Abstract:
Electrostatic Discharge (ESD) poses significant challenges to the reliability of high-speed and high-density storage systems. This presentation delves into practical strategies for mitigating ESD, focusing on innovative design and engineering solutions. Key topics include the implementation of ESD design approaches for different storage product lines, enhanced resistance analysis, grounding techniques, and optimized circuit designs to minimize ESD vulnerability. This session also covers real-world case studies demonstrating successful ESD mitigation in cutting-edge storage technologies.

Manohar Seetharam

Samsung Semiconductor India Research

Talk Title:
A Robust ESD Protection Scheme for High-Speed Serial Interface in 3nm MBCFET Technology

Abstract:
Low power wireline circuits have derived substantial benefit from FinFet, GAA and MBCFET process nodes. However, these processes are also more sensitive to ESD events. Simple incorporation of a T-coil was traditionally sufficient to overcome this problem and trade-off with high-speed performance. The proposed ESD methodology and scheme meets greater than 250V & 7A CDM strike while supporting more than 24Gbps speed on the data pins. The design was fabricated in Samsung 3nm MBCFET process and the Silicon performance verified. The paper also discusses the challenge posed by high resistive metal and vias used in the 3nm process.

Mr. Sharath B N

COMSOL

Talk Title:
Multiphysics Simulation for the Semiconductor Industry

Abstract:
Modeling and simulation of semiconductor devices, their manufacture, and the components and infrastructure surrounding them has become more complex due to a number of factors, such as the reduction in the size of semiconductor devices, the general competitiveness of the industry, and requirements for increasing their performance. The ability to accurately model these devices and associated manufacturing technology increasingly requires a multiphysics approach to define and analyze their physical aspects. COMSOL Multiphysics®, along with its add-on products, have been widely used for design and optimization in semiconductor processing. Join us in this session to learn more about the use of multiphysics simulation for the modeling and simulation of semiconductors and semiconductor processes. The speaker will also discuss the role of multiphysics simulation in electrostatic discharge applications and thermal management of electronics.