Sabarigresan Murugan

Application Scientist

Park Systems India

Talk Title:
Nanoscale Failure analysis using AFM

Abstract:
Industry standards now demand near-zero manufacturing downtime, making root-cause analysis for any production defect critical. Advanced Atomic Force Microscopy (AFM) addresses this by enabling nanoscale failure analysis, dopant profiling, and rigorous quality control. This study explores key electrical AFM modes - including Scanning Capacitance Microscopy (SCM), Scanning Spreading Resistance Microscopy (SSRM), and PinPoint Electrical AFM (iAFM) - for high-resolution, precise carrier characterization. Furthermore, we demonstrate that high-vacuum environments, such as the Park NX-Hivac system, significantly reduce contact force, eliminate sample oxidation, extend tip lifetime, and enhance signal-to-noise ratios compared to ambient operations. Additionally, operational enhancements like QuickStep scanning and specialized sample-tilting wedges successfully optimize measurement throughput, minimize thermal drift, and enable accurate characterization of complex device topographies, including FinFETs and vertical sidewall structures.

Bio:
Application Scientist for Park Systems India and has a high level of experience in handling Atomic Force Microscopes (AFM ) and Ph.D. in Materials science and metallurgical Engineering at the Indian Institute of Technology (IIT) Hyderabad, with his research focused on multifunctional thin film fabrication techniques. He has a strong academic background, having completed his M.Tech in Materials Science with a Gold Medal from the Central University of Tamil Nadu and B.Tech in Mechanical Engineering. Sabarigresan’ s research interests lie in developing advanced thin films with diverse applications, and he brings hands-on expertise in fabrication and characterization. During his Ph.D., he extensively used park systems AFM, and he has vast experience on most of the functional modes like PFM, EFM, CP-AFM, KPFM, STM and MFM.

M. M. C. Kishore

Founder and CEO

Global Marketing Services (GMS)

Talk Title:
Tools for Emerging Technologies in chip fabrication, assembly and characterisation.

Abstract:
Emerging technologies in chip fabrication, assembly, and characterization are driving a new era of semiconductor innovation, enabling higher performance, energy efficiency, and scalability. The rapid evolution of nanoscale devices, heterogeneous integration, and advanced packaging demands novel tools that can address the challenges of precision, throughput, and reliability. In fabrication, processes such as lithography, wet process and other process are critical . Assembly processes are being transformed by 3D integration, wafer-level packaging, and micro-bump bonding, which require ultra-accurate alignment, defect-free interconnects and temporary bonding and debonding . Characterization tools, including wafer warp, x-ray, C-SAM are essential for structural properties for driving quality and reliability. Together, these tools form a synergistic ecosystem that supports the design and deployment of advanced chips for applications in artificial intelligence, quantum computing, and high-performance communication systems. This talk explores the state-of-the-art tools across these domains, highlighting their role in overcoming scaling bottlenecks and enabling the future of semiconductor technology.

Bio:
M. M. C. Kishore is the Founder and CEO of Global Marketing Services (GMS), a Bengaluru-based company that has become a vital bridge between global technology innovators and India’s semiconductor, EV battery, and microelectronics ecosystem. With over two decades of leadership, he has positioned GMS as a trusted partner for academia, startups, and industry.

• Founder & CEO of Global Marketing Services (GMS): Established over 25 years ago, GMS connects international technology leaders with Indian customers in semiconductors, EV batteries, MEMS, photonics, and advanced packaging.
• Education: Holds a Bachelor of Science in Instrumentation from Bangalore University.
• Global Partnerships: Represents over 40 international brands, including ADT (Israel), Azur Space Power (Germany), Akrometric (USA), ClassOne Technology (USA), Cost Effective Equipment (USA), F&S Bondtec (Austria), F&K Delvotec (Germany), Nippon Avionics (Japan), NTK (Japan), and many more.
• Vision 2030: Aims to leverage semiconductor expertise to empower startups, SMEs, and OEMs in building advanced EV technologies aligned with India's EV 2030 mission.
• Technology Ecosystem Builder: GMS has supported institutions like IISc, DRDO, DOS, as well as commercial fabs and OSATs, enabling access to cutting-edge tools and solutions.
• Emerging Technologies Focus: Actively engaged in MEMS, compound semiconductors, photonics, and quantum technologies, positioning India within the global semiconductor supply chain.
• Entrepreneurship & Innovation: Recognized for transforming challenges in logistics, awareness gaps, and market timing into opportunities through strong industry networks and local expertise.
• Mentorship & Collaboration: Works closely with academia, government, and industry to foster India's deep-tech ecosystem.
• Track Record: Successfully delivered over 1,000 technology solutions across diverse industries.

Prashant Gajbhiye

Staff Engineer - ESD Engineer

Marvell Technology

Talk Title:
3D PERC Verification in Advanced Packaging

Abstract:
The increasing adoption of advanced semiconductor technologies and heterogeneous integration has led to the widespread use of multi-die packaging architectures. Ensuring ESD reliability and correct connectivity across such complex systems is a critical challenge. 3D Physical Electrical Rule Checking (3D PERC) provides a comprehensive framework for verifying electrical behavior, connectivity, and reliability across stacked designs consisting of multiple dies, interposers, and substrates. In this work, a methodology for 3D PERC-based system-level verification is presented, focusing on key aspects such as point-to-point (P2P) connectivity checks, topology validation, and resistance-based path verification. The approach enables accurate validation of signal paths and ensures correct electrical behavior across multiple layers of integration. Additionally, ESD-related verification, including discharge path validation and protection network analysis, is incorporated to ensure robust design reliability. The study also highlights challenges associated with 3D PERC verification, including complex multi-layer connectivity, large-scale power/ground networks, and debugging of topology violations. Techniques such as 3D-aware rule configuration, optimized rule implementation, and efficient debug methodologies are applied to improve verification accuracy and runtime efficiency. The proposed approach enables early detection of connectivity and reliability issues and provides a scalable and reusable verification solution for advanced multi-die and packaging technologies. This contributes to improved design robustness and reduced turnaround time in modern semiconductor design flows.

Bio:
I am Prashant Gajbhiye, a Staff Engineer in Bangalore with 5+ years of experience in the VLSI industry, specializing in ESD-PERC runset development and signoff verification. I have expertise in developing and validating ESD verification methodologies, including Topology Checks, P2P Connectivity Checks, Current Density Analysis, and LVS-based verification, ensuring robust and reliable semiconductor designs. My experience spans physical verification, electrical reliability, and signoff flows, collaborating with design, foundry, and product teams to deliver high-quality verification solutions. I am also passionate about advanced packaging and 3D IC verification, with a strong interest in 2.5D/3D integration, chiplet architectures, and system-level reliability.

Srinivasamuni Adepu

Senior IO Layout Manager

Mixed Signal IP group, ASIC, SanDisk

Talk Title:
ESD protection:Layout Challenges, Verification and Silicon learnings

Abstract:
Electrostatic Discharge (ESD) protection continues to be a critical reliability requirement for advanced-node SoC and IO designs. As IO pad-rings become denser and designs include multiple voltage and power domains, ESD implementation must address layout, routing, verification, and silicon robustness together. This talk will discuss practical layout challenges in IO and pad-ring design, including ESD current path optimization, clamp placement, routing considerations, multi-voltage and multi-power domain handling, and metal/via reliability. It will also cover ESD verification and sign-off methodologies used to identify protection gaps and improve closure confidence. The session will share silicon failures and lessons learned, along with best practices adopted in production designs. The goal is to provide practical guidance for improving ESD robustness, reducing debug cycles, and increasing first-pass silicon confidence.

Bio:
Srinivasamuni Adepu is a Senior Manager in Analog & Mixed-Signal Engineering at SanDisk, with over 16 years of experience in IO library and custom IP layout development. He has led the development of IO libraries and pad-ring solutions for multiple memory controller SoCs, with expertise in ESD protection, advanced-node IO layout design, physical verification, and silicon ESD signoff.

Harshit Dhakad

Intel

Talk Title:
From simulation to silicon: RF ESD design and characterization for Wifi transceiver

Abstract:
Every Wi-Fi transceiver chip that ships in a laptop or smartphone, carries a hidden design battle — one fought between two competing demands. On one side, the RF circuits need clean, low-loss signal paths to deliver the sensitivity and linearity that modern Wi-Fi standards require. On the other, every chip must survive real-world electrostatic discharge events that can instantly destroy unprotected devices. As CMOS technology scales to smaller nodes, this problem only gets harder to resolve — the design window between adequate ESD robustness and acceptable RF performance keeps shrinking. This talk walks through the complete journey from design intent to ESD qualified silicon and focusses a practical, experience-driven perspective on building ESD protection that a Wi-Fi transceiver can actually live with — robust enough to pass qualification, transparent enough not to compromise the RF performance that the product was designed to deliver.

Bio:
Harshit Dhakad is Principal Engineer, Electrostatic Discharge and Latch up protection design at Intel Technologies India Pvt. Ltd, with combined experience of 21 years at Intel PESG and former iCDG/Infineon Wireless. Harshit received the B.E. degree with honours in Electronics and Telecommunication Engineering from Ujjain Engineering College Ujjain, India, in 2003. He received the Masters in Technology (M. Tech.) degree at the Indian Institute of Technology, Delhi, India in Integrated Electronics and Circuits in 2005. He leads ESD development, product support and enablement encompassing diverse range of foundry technologies including advance GAA, FINFET and planar CMOS. Harshit specializes in developing and implementing area, capacitance and leakage efficient ESD architecture and custom ESD solutions for RF, mm-wave and HS serial interfaces, and ESD verification of complex SoC’s. These cutting edge ESD solutions are utilized by several Intel and Mobileye products. He is member of executive committee of India ESD Workshop and has filed 12 patents and authored several technical papers on ESD.

Dr. Vasu Duvvury

Professor (Retired)

University of North Texas, USA

Talk Title:
Art and Symbolism of the Hand Fan: Its Global and Historical Importance

Abstract:
At the mention of a 'hand fan', one immediately thinks of a mundane and ordinary object that one uses to cool oneself on a warm and summery day. But the utilitarian and decorative fan in many styles has been used by different cultures across civilizations as an aesthetic and cultural object since very ancient times to signify a variety of things in social and religious contexts like status, artistry, social and cultural identity. This talk will explore this fascinating topic with illustrations and pictures of fans both globally and historically.

Bio:
Dr. Vasu Duvvury received her M.A. and Ph.D. in Anthropology from Rice University at Houston, Texas. She also holds an M.A. in English. Her PhD thesis was published as a book entitled, Play, Symbolism, and Ritual. She is currently working on two anthropology books on Asia. She is also an award-winning photographer and some of her photographs and photo-paintings can be seen at her website, vasuduvvury.com

Thomas Tatry

Application Engineer

SENTECH Instruments, Germany

Talk Title:
SENTECH Instruments - Experts in Plasma process and thin Film metrology

Abstract:
SENTECH has over thirty years of experience developing and manufacturing plasma process technology systems and thin film metrology tools for research and development and industrial production worldwide. Our robust systems focus on the etching, deposition, and characterisation of thin films in semiconductor technology, microsystems technology, photovoltaics, nanotechnology, and materials research.
The SENTECH flexible and reliable plasma etch and deposition systems, including atomic layer deposition equipment, support state-of-the-art processes and applications. Our tools and systems are used worldwide for applications in the fields of nanotechnology, micro-optics, sensor technology, photonics, and optoelectronics.
SENTECH offers a wide range of spectroscopic ellipsometers, laser ellipsometers, and reflectometers for measuring the thickness and optical constants of very thin layers or layer stacks. SENTECH has achieved particular success in the field of industrial quality control, for example in photovoltaics, 5G devices, and sensor technology.
For more information or to contact a member of the team, please visit our website www.sentech.de

Bio:
Thomas Tatry holds a Master's degree in Materials Science with a specialisation in Semiconductor Technologies from France. With over 15 years of industry experience in Germany, he has worked in various roles spanning plasma etch process development, tool automation, and application engineering. Thomas spent 5 years at Infineon Technologies focusing on plasma etch process development and transfer, followed by 5 years in the automation tool industry as a project manager. Since 2016, he has been an Application Engineer at SENTECH Instruments, specialising in plasma process solutions. Thomas’s work bridges the gap between advanced process technologies and practical industrial applications.