ESD Design Essentials

Date: January 8-9, 2015

Venue: The Oberoi, 39, Mahatma Gandhi Road, Bangalore, Karnataka - 56000, INDIA

Instructors: Harald Gossner, Intel; Prof. Mayank Shrivastava, Indian Institute of Science

This two-day workshop consists of concentrated versions of twelve ESD tutorials which comprise the following topics:

• ESD On-Chip Protection in Advanced Technologies
• SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits
• EOS/ESD Failure Models and Mechanisms
• On-Chip ESD Protection in RF Technologies
• Charged Device Model Phenomena and Design
• Latch-up Physics and Design
• Circuit Modeling and Simulation for On-Chip Protection
• Troubleshooting On-Chip ESD Failures
• Device Testing–IC Component Level: HBM, CDM, MM, and TLP
• Impact of Technology Scaling on ESD High Current Phenomena and Implications for Robust ESD Design
• Transmission Line Pulse
• Measurements: Parametric Analyzer for ESD On-Chip Protection
• System Level ESD/EMI: Testing to IEC and other Standards

Why to learn ESD Device and Circuit Design?

Predominant failure mechanism: It is estimated that above ~25% of component failures are due to Electrical Overstress (EOS) and Electrostatic Discharge (ESD).

Changing Technologies: Constantly changing technologies make the ESD protection design challenging. Learning from past Si technologies is no more sufficient.

Reliable Chips: For reliable operation of Integrated circuits ESD continues to be a major concern.