Keynote & Invited Speakers
Dr. Harald Josef Erhard Gossner
Intel Deutschland GmbH
Talk Title:
The Picosecond Challenge in CDM Testing–endangering ESD Robustness of Highspeed Interfaces
Abstract:
Ultrafast transients during a Charged Device Model (CDM) ESD test have led to puzzling fails of high speed interfaces. It has been found that package and IC design solutions for high speed interfaces with a Nyquist frequency far above 5 Ghz become more and more transparent for CDM pulse slopes below 100 ps. While this was not considered as relevant in previous designs the combination of ultra-fast pulse transients, high bandwidth of the transmission channel to the gate oxide and the high overvoltage sensitivity of gate oxides in sub 3nm CMOS nodes causes a drop in ESD robustness far below a 250 V CDM target. The talk will present the effect and the modelling approach to correctly capture this effect during the ESD protection design phase.
Dr. Gianluca Boselli
Texas Instruments
Talk Title:
System-Level ESD design challenges in HV Automotive Applications: process, IP and system co-design perspective
Abstract:
The trend towards society’s “smart-electrification” is driving the need for ESD immunity at system-level. IEC 61000-4-2 defines how to perform the Electrostatic discharge immunity test at system level. To protect against these events, until fifteen years ago, ad-hoc ESD protections (TVS – Transient Voltage Suppressors) were implemented at board/ system - level in proximity of the connectors interfacing with the “external world”. However, a new trend of implementing system-level robustness at component-level (i.e. on-chip) is quickly becoming standard practice, mainly stemming from the desire to reduce system/board design cost. While on paper this may sound as a logical step, it poses enormous challenges to the component ESD Designer in that: 1) IEC 61000-4-2 is NOT applicable to component-level, so every company is struggling to understand/design proprietary characterization methods at component level to extrapolate performance at system-level. 2) ESD Designers are now responsible for the performance of systems they do not build nor, in many cases, they know anything about. In the automotive world, situation is even more challenging. In addition to ESD immunity at system-level, there is a plethora of other requirements against immunity to Electrical Disturbances and immunity to RF disturbances that must be met. This talk will address the ESD Design challenges stemming from automotive system-level ESD specs, along with the trade-offs between ESD Design and EMC Immunity requirements.
Dr. Charvaka Duvvury
iT2 Technologies
Talk Title:
Exploring Machine Learning for ESD Data Analysis
Abstract:
Can Machine Learning (ML) take us into greater efficiency of IC ESD Evaluation? What we now know of machine learning has taken on a wide interest in the semiconductor industry. One prime area of exploration of ML would be in ESD data characterization and analysis. This seminar will present ML opportunities for ESD from I-V curve data interpretation for HBM and CDM evaluation to possible applications with TLP and VfTLP data investigations for design purposes. A case study on how IV curve data was analyzed to demonstrate the concept of machine learning to recognize patterns and the potential for predictability from new data on new sets of devices from measurements. Finally, the talk will outline future opportunities of ML in ESD applications.
Prof. Elyse Rosenbaum
University of Illinois Urbana-Champaign
Talk Title:
ESD Design for High-speed Wireline IOs in Advanced CMOS Technologies
Abstract:
Wireline data rates have reached tens and even hundreds of Gb/s. In each new process technology, it is necessary to develop highly-efficient ESD protection devices, which can safely shunt a large current per unit of (parasitic) capacitance. It is also necessary to jointly optimize the front-end circuitry both for signal integrity and ESD reliability, an endeavor that requires extensive circuit simulations. ESD over-design is not feasible for high-speed IOs and thus the accuracy of the ESD simulations is paramount. Unfortunately, the compact models included in a PDK are not accurate at ESD current levels. Furthermore, the ESD current has a very high slew rate, and an RC extracted netlist will not capture the inductive voltage drops. This presentation will demonstrate that ESD models enable the design of reliable high-speed IO circuits.
Prof. Mayank Shrivastava
Professor, Indian Institute of Science, Bangalore
Talk Title:
Predictive TCAD-Based ESD Design without Foundry Data
Abstract:
In the realm of ESD device engineering in advanced and technologically complex nodes, the ability to predict and design robust ESD protection concepts is paramount. Traditional ESD design approaches often rely heavily on foundry-specific data/process information, which can be a limiting factor in terms of accessibility and flexibility. This talk presents an innovative methodology that leverages Technology Computer-Aided Design (TCAD) simulations to predict ESD performance without the need for proprietary foundry/process data. We will delve into the principles and advantages of TCAD-based modeling, demonstrating how these simulations can accurately replicate physical phenomena and predict device behavior under ESD stress conditions. The discussion will cover the integration of predictive modeling techniques, parameter extraction, and the calibration of TCAD models to achieve high-fidelity results. By eliminating the dependency on foundry/process data, this approach not only democratizes ESD design but also accelerates the development cycle, enabling designers to quickly iterate and optimize ESD protection solutions.
Dr. Matteo Buffolo
University of Padova - Department of Information Engineering, Italy
Talk Title:
Robustness of GaN-based LED against EOS events and ESDs
Abstract:
Over the last twenty years, the reliability of GaN-based visible LEDs has vastly improved, mostly due to optimizations in device structure and in the epitaxial growth, to a point where a useful lifetime of the solid-state source in excess of tens of thousands of hours can be achieved. For these mature devices, extrinsic factors, such as EOS and ESD events, represent a major lifetime-limiting factors during operation on the field. This talk investigates from a physical standpoint the impact of overstress events on GaN-based LEDs, and reports on the device-level mitigation strategies that can be adopted to improve LED robustness against such phenomena.
Dr. Teruo Suzuki
Socionext Inc
Talk Title:
Consideration based on ESD applied waveform in High-Speed IF using T-Coil
Abstract:
The T-Coil is one of the indispensable circuits in high-speed IF circuits and can reduce the effect of parasitic capacitance in ESD protection circuit. We fabricated a TEG equipped with ESD protection circuit, using the T-Coil driven by the state-of-the-art CMOS technology and investigated its performance. CDM failed at about 3.5A, VF-TLP failed at 2.2A, and the simulation reproduced those measurements. The effect of T-Coil mutual induced voltage is particularly pronounced in VF-TLP and is inconsistent with CDM. Since VF-TLP (TLP) is a tool for ESD design, ESD designers should consider this finding especially for leading-edge CMOS technology processes. There have been some reports of miscorrelation between TLP and ESD measurements, and the T-Coil is yet another case.
Dr. Dolphin Abessolo Bidzo
NXP Semiconductors, The Netherlands
Talk Title:
Electronic Design Automation (EDA) Layout Verification Methodology for Charged Device Model (CDM)
Abstract:
ESD Electronic Design Automation (EDA) verification tools have become instrumental to the design and verification flow of integrated circuits (IC’s). This trend has been mostly driven by the extraordinary development and increasing complexity of IC’s in the past few years. With the downscaling of the process technology nodes, CDM represents the main ESD threat for IC’s in assembly lines. Furthermore, increasingly demanding product performance with necessary ESD reliability requirements make it very challenging to achieve first-time-right silicon for both functional and ESD exigency. In that context, the use of ESD verification tools to de-risk IC designs before tape-out or for debugging purpose has become critical. ESD verification is not limited to circuit topology analysis. In order to improve its coverage, further geometrical, layout-based checks and simulations are required to verify the proper construction and implementation of ESD protection devices. Complementary to the topological ESD checks, these CDM layout simulations are meant to identify weak ESD paths, to perform a detailed analysis of back-end metallization and to spot victim devices (e.g. gate oxide of MOS devices) exceeding breakdown voltages under CDM like circumstances. The layout verification for CDM is performed at full chip level typically. In this presentation, the methodology of the state of the art CDM layout simulations tools is described, real life case studies are presented and the outlook towards future developments is discussed.
Dr. Kranthi Nagothu
Texas Instruments
Talk Title:
On-chip protection Design Challenges for system level ESD
Abstract:
In this presentation, unique failure mechanisms in high voltage Silicon Controlled Rectifiers (SCR) under IEC stress are discussed. In one case, the presence of a common mode choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in DeNMOS based SCR. In second, Air-Discharge IEC failure in Bi-Directional SCRs that are sensitive to IEC measurement conditions via the pulse rise time are investigated. 3D-TCAD simulations are used to develop the physical Insights of the failure and propose the device level engineering solutions to mitigate the IEC failures.
Christopher Almeras
Raytheon, an RTX Business
Talk Title:
Risk Mitigation in Manufacturing of High Reliability Products
Abstract:
Electronics manufacturing is the engine that keeps the world’s motor running. Designs of circuit cards and devices continue to become more complex and provide greater power and capabilities to everything we depend on. As the complexity increases, so does the requirements to protect these devices from ESD during manufacturing. When you have product that must work every time, further care needs to be taken to ensure the product is protected throughout the build cycle. In this presentation, we will discuss how the ESD TR19 document on Protection of High Reliability parts, builds on the foundation provided by ANSI/ESD S20.20 to provide further risk mitigation. We will also help answer questions regarding appropriate application and implementation strategies.
Ms. Yang Yanjing
ThermoFisher Sci/Singapore
Talk Title:
Failure Analysis workflow for Advanced Packing and Power Semiconductor Device
Abstract:
As semiconductor packaging evolves with technologies like 3D-IC, 2.5D, and wafer-level packaging, new reliability and performance challenges emerge, such as die-level defects, TSV formation issues, and bonding problems. Identifying these faults is crucial yet complex, requiring advanced techniques for rapid, precise, and accurate data. This talk will delve into the failure analysis workflow for advanced packaging and power semiconductor devices. It will cover process metrology, characterization challenges, and industry-leading workflows for assembly failure isolation and complete die analysis. Emphasizing techniques for high sample throughput, high resolution, and unmatched automation, the presentation will showcase how to accelerate failure analysis and reduce time-to-data, enhancing device performance, reliability, and yield.
Mr. Mototsugu Okushima
Renesas Electronics, Japan
Talk Title:
Efficient CDM Protection Design for Cross Power Domain of Analog/RF block in Finfet Technology
Abstract:
Analog/RF circuit blocks that need noise isolation from digital block or each other are increasing more. To protect the vulnerable transistor in finfet technology, power clamp between cross domain is useful. However, increasing number of isolated blocks costs large area for the ESD clamps. To suppress the area increase, this presentation gives an efficient CDM protection design for cross-domain interface circuits especially using "internal cross clamp" as voltage divider between the internal power supply node of analog circuits and the digital GND node. The proposed protection circuit meets high CDM current request from large package IC with finFET technology while suppressing the area increase for analog/RF circuit blocks.
Dr. Hossam Sarhan
Siemens EDA, France
Talk Title:
Ensuring Sign-off Design Reliability: Navigating Complex Requirements using Calibre® PERC™
Abstract:
Conservative design rules and constraints are often used in reliability verification flows. Foundry qualified and supported rule decks, augmented by custom checks, are essential to establishing this reliability baseline, not only to guide improvements, but also to establish best practices with internal and 3rd party IP through full-chip sign-off. When verifying the robustness of your electrostatic discharge (ESD) protection strategy in your design, it is essential to ensure sufficiently sized devices and interconnects while understanding ESD margins with SPICE-accurate full-chip simulation. The Calibre PERC reliability platform automatically combines netlist and layout information to perform targeted electrical checks that consider the context of the design intent for both layout-related and circuit-dependent checks. We will explore exciting challenges and verification developments to ensure reliability in your designs.
Prof. David Pommerenke
Institute of electronics, Graz university of technology, Austria
Talk Title:
System Efficient ESD Design
Abstract:
This talk discusses the protection of I/O from ESD. In the past, transient voltage protection could be selected from a data sheet. However, the shrinking of the design window due to smaller IC feature size combined with data rates > 50 Gbit/sec forces design by simulation. The system efficient ESD design process creates models of the TVS and the IC. In combination with passive components or traces, a complete model is created that allows ESD robustness to be predicted. The talk will explain the overall process, the measurement techniques used to gather the data needed for modeling, and the models themselves. It will show the capabilities and limitations of these methods and enable the audience to
follow the process.
Dr. Charvaka Duvvury
iT2 Technologies
Talk Title:
Green ESD: Efficient Test Methods to Save Time and Effort During Qualification
Abstract:
ESD qualification test methods often consume significant testing times to meet HBM and CDM spec requirements. This is especially the case for products with multiple power domains and/or IC packages with high pin counts. During the last several years improvements have been demonstrated to significantly reduce testing times by employing more efficient test methods which have been approved by JEDEC. This seminar will review these methods that include novel sampling approaches for cloned IO pins as well as outlining techniques for avoiding misleading interpretation of CDM data often resulting in cumulative effects. The seminar will conclude with an outlook into more advanced statistical methods.
