Keynote & Invited Speakers
Dr. Matteo Buffolo
University of Padova - Department of Information Engineering, Italy
Talk Title:
Effects of ESDs on GaN LEDs: a device perspective
Abstract:
Over the last 25 years, the reliability of LEDs based on nitride semiconductors has vastly improved, allowing state of the art devices emitting in the visible range to reach useful lifetimes in excess of tens of thousands of hours. Hence, for these technologies, extrinsic overstress events, such as ESDs, represent the major cause of failure on the field. While previous studies have somehow investigated the relation between overstress and sudden failures, a lack of literature on the potential latent damage provoked by the non-destructive overstress events is missing. This talk primarily aims to investigate this topic from a physical standpoint, by also leveraging some recent results obtained on visible InGaN/GaN LEDs.
Bio:
Over the last 25 years, the reliability of LEDs based on nitride semiconductors has vastly improved, allowing state of the art devices emitting in the visible range to reach useful lifetimes in excess of tens of thousands of hours. Hence, for these technologies, extrinsic overstress events, such as ESDs, represent the major cause of failure on the field. While previous studies have somehow investigated the relation between overstress and sudden failures, a lack of literature on the potential latent damage provoked by the non-destructive overstress events is missing. This talk primarily aims to investigate this topic from a physical standpoint, by also leveraging some recent results obtained on visible InGaN/GaN LEDs.
Dr. Sergej Bub
Nexperia Germany GmbH
Talk Title:
ESD Protection and ESD Simulation for Automotive Interfaces
Abstract:
This invited talk examines ESD protection for automotive interfaces using System Efficient ESD Design (SEED) simulations and best-practice matching strategies for off- and on-chip solutions to predict and optimize system-level ESD robustness. It introduces the SEED methodology, reviews common automotive protection concepts and tools, and discusses typical failure scenarios and system model setups. Emphasis is placed on behavioural modelling of external ESD devices, including parameter extraction and tuning based on Transmission Line Pulse (TLP) data. Finally, SEED simulations are demonstrated for modern automotive Ethernet and CAN buses, highlighting the impact of component placement, common-mode chokes, and matching challenges between off- and on-chip protection in high-speed systems.
Bio:
Sergej Bub is a Principal System Level ESD expert at Nexperia Germany GmbH in Hamburg. He holds an M.Sc. in Electrical Engineering from the Technical University of Hamburg, specializing in nanoelectronics and microsystems. With over 10 years in R&D, he focuses on ESD protection and filtering, including modelling, simulation, and development of ESD protection solutions for System Efficient ESD Design (SEED) in high-speed systems across automotive, mobile, consumer, and computing applications, alongside project management activities.
Dr. Charvaka Duvvury
iT2 Technologies
Talk Title:
Celebrating 20 Years of Influencing ESD Targets, Standards, and Test Methods
Abstract:
Founded in 2006 by just four companies, the Industry Council on ESD Target Levels has made significant strides in advancing the ESD community. This anniversary presentation will summarize the early achievements and the latest developments in the work over the last 5 years. First, we review how the HBM and CDM changes were initiated, and the overwhelming data analysis that overcame the most common resistance to lowering these target levels, which are critical for high-speed performance circuits. The talk will then move on to other topics in EOS and System Level misunderstandings, and the critical achievements that establish clear insight into these areas. The most important part of the seminar will describe the complex topic of “transient Absolute Maximum Rating” (tAMR) and the controversy surrounding it, which has led to a clearer understanding after nearly 5 years of debate. For both EOS safety and IC customer applications, a tAMR that allows pulses exceeding the common AMR is critical. Another recent important topic has been “Direct Pin System Level ESD Testing”. These two topics are the crowning achievements of the Council since 2020 and require thorough industry appreciation to improve the reliability of electronic systems into the next decade.
Bio:
Charvaka Duvvury was a Texas Instruments fellow, known for pioneering development work in ESD design. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the ESD Association. He has been a co-founder of the Industry Council on ESD Target Levels since 2006. In 2015, he co-founded iT2 Technologies, which uses a software engine to enable rapid ESD data analysis. Charvaka is also a Life Fellow of the IEEE.
Dr. Mirko Scholz
Infineon Technologies AG, Germany
Talk Title:
The ESDA Technology Roadmap
Abstract:
The ESDA technology roadmap aims to support and guide the daily work of ESD and latchup experts in the worldwide industry and academia. It discusses ESD target level and their impact on ESD control practices. Next to regular updates on ESD testing standards the focus of the document is on technical challenges in our industry. In this talk we will provide an update on the 2027 edition and give an outlook on the ESD and Latchup challenges for the coming years.
Bio:
Dr. Mirko Scholz is a Principal Engineer ESD Development at Infineon Technologies AG in Neubiberg/Germany. From 2005 until 2019, he has been an ESD researcher at imec in Leuven/Belgium. He was the General Chair of the 2025 ESD Symposium and is heading the Advanced Topics committee of the ESDA.
Prof. Susanna Reggiani
University of Bologna
Talk Title:
TCAD-based physical modeling of SCR-LDMOS improving ESD protection with high holding voltages
Abstract:
Emerging applications, such as automotive electronics, power management, driver integrated circuits, require ESD protection cells with relatively high trigger and holding voltages in a wide range of operating biases, leading to the need for a family of ESD cells providing optimized performance and minimum occupation area, which is still very challenging. The key element in BCD technology is the LDMOS device with additional integrated SCR. To establish the relevant trade-off between the key parameters, a figure of merit (FOM) is adopted along with dynamical crucial parameters. 2D/3D TCAD simulations are required for a deep physical interpretation of the device behaviour under high injection regimes up to the thermal failure. The proposed physically-based approach will be detailed with some recent examples.
Bio:
Susanna Reggiani received the Ph.D. degree in Electrical Engineering from the University of Bologna, Italy, in 2001. Since 2002 she is with the Department of Electrical, Electronic, and Information Engineering (DEI) and with the Advanced Research Center for Electronic Systems (ARCES). In 2020 she became Full Professor at the University of Bologna. Her scientific activity has been devoted to the physics, modeling and characterization of electron devices, with special emphasis on transport models in semiconductors.
Prof. Isabella Rossetto
University of Bologna
Talk Title:
Investigation of ESD effects on normally-off p-GaN gate power HEMTs by TLP analysis and numerical simulation
Abstract:
In this work we will present the effect of electrostatic discharge (ESD) on GaN power HEMTs with Schottky gate metal. The device robustness and the impact of the device geometry is discussed. The root causes of the degradation processes are investigated by transmission line pulse (TLP) system, numerical simulation and deep level characterization techniques.
Bio:
Isabella Rossetto is an associate professor at the University of Padova. After post doc she has been working at STMicroelectronics from 2017 to 2025, focusing on the research and development of oxides and dielectrics, and on the reliability of GaN electronic devices. Her research topics at the University of Padova are characterization and reliability of GaN electronic devices aimed at power electronics and radiofrequency systems
Dr. - Ing. Andreas Hardock
Nexperia Germany GmbH
Talk Title:
Optimizing Signal Integrity when Using ESD Protection Devices
Abstract:
This part focuses on practical methodologies to preserve signal integrity (SI) while implementing effective ESD protection in high-speed automotive and mobile interfaces. It emphasizes the trade-offs between SI performance and ESD robustness in bandwidth-limited and impedance-controlled systems. A simulation-driven approach is applied using SPICE, IBIS/AMI, and 3D EM tools to evaluate key metrics such as insertion loss, return loss, impedance discontinuities, and eye diagram degradation, with strong correlation to measurement results. Topics include selection and modeling of low-capacitance ESD devices, parasitic effects, and co-design of terminations and filtering networks. PCB layout best practices address parasitics and return paths. Case studies from Ethernet and SerDes illustrate optimization of ESD protection and passive networks while maintaining SI performance.
Bio:
Andreas Hardock earned a degree in Nanostructure Technology from the University of Würzburg and a Ph.D. from TU Hamburg-Harburg. He began as an EMC engineer at Behr-Hella Thermocontrol in 2015, worked at Continental Automotive (2016–2020) as a hardware architect focusing on SI, PI, EMC, and ESD. Since 2020, he is with Nexperia in product applications. He is a Senior IEEE member, active in the EMC Society and German EMC Chapter, serving as Treasurer since 2020.
Dr. Harald Josef Erhard Gossner
Intel Corporation, Germany
Talk Title:
ESD Targets and Testing methods for D2D Interfaces
Abstract:
Complex heterogeneously integrated system in package with hundred thousand to millions of die-to-die interfaces are key for innovative, high-performance Ai CPU and GPU components. Also, across the full spectrum of ICs the usage of chiplets applying die-to-die interfaces will become a driver of innovation. A critical aspect for design is the ESD protection concept where the sheer number of die-to-die interfaces strongly limits the area for protection and the parasitic capacitance. Industry Council on ESD Target levels has proposed a roadmap to 5 V CDM moving to 3V CDM from 2028 on as target level for die-to-die interfaces. An even more fundamental issue is the inability to perform an exhaustive ESD qualification test of these dies due to extremely small pitch of the hybrid bonds of less than 3 µm and the challenge of testing millions of interfaces for one sample. These fundamental questions have recently bene addressed by research and standardization efforts. These are affecting already todays IP and SoC design. The current status and an outlook are provided by the talk.
Bio:
Harald Gossner is leading system ESD design at Intel as Senior Principal Engineer. Before joining Intel in 2011, he has worked with Siemens and Infineon Technologies. He is a founder of Industry Council on ESD Target Levels, President Emeritus of EOS/ESD Association, IEEE Fellow and editor of IEEE EDL. As member of advisory boards, he consults the Bavarian government and Fraunhofer institutes and leads the government-funded Semiconductor-X project building a resilient supply chain of semiconductors.
Joost Willemen
Infineon Technologies, Germany
Talk Title:
Characterizing TVS Devices for Antenna Protection: ESD Robustness Meets RF Linearity
Abstract:
"The increasing integration density of modern RF systems is driving growing demand for dedicated ESD protection at antenna ports of mobile devices. TVS devices represent a promising protection solution, but their suitability for antenna applications extends beyond ESD robustness and clamping performance alone. RF linearity is a critical requirement, as nonlinear device behavior generates unwanted harmonics and intermodulation products that can degrade system performance. This talk examines TVS devices for antenna ESD protection with emphasis on characterization methods and measured device behavior. Key approaches for assessing linearity and harmonic generation are presented, and the underlying mechanisms driving nonlinear behavior are discussed. The results provide insight into the relevant device parameters that determine TVS suitability for RF antenna protection applications."
Bio:
Joost Willemen is Senior Principal Engineer for ESD Development at Infineon Technologies in Munich, Germany. He is technical lead for TVS/ESD protection devices and related discrete devices, with previous ESD engineering roles at Infineon and Robert Bosch. He earned his Master’s and PhD in electrical engineering from Delft University of Technology. His research focuses on ESD device physics and characterization. Joost has authored numerous publications and actively contributes to IEEE, EOS/ESD, and related industry committees.
Mr. Christopher Almeras
Raytheon, United Statwa
Talk Title:
Optimizing the Effectiveness of an ESD Control Program Through Enhanced Training
Abstract:
ANSI/ESD S20.20 requires an organization’s ESD Control Program to establish a Training Plan that includes initial and recurrent training. Despite the importance of this requirement, training is one of the most underutilized tools in the protection of ESD sensitive items. This presentation covers additional training strategies to optimize the effectiveness of an ESD Control Program.
Bio:
Christopher is the current RTX Corporate ESD Council Chair and SME. His work experience has included Process Enginering roles along with his ESD responsibilities. He is an ESDA Certified ESD Program Manager and continues to be active in industry ESD standards. He holds a BS of Mechanical Engineering from Purdue University and an ME in Industrial Engineering with a focus on Manufacturing Systems from Oklahoma State University.
Prof. David Pommerenke
Graz University of Technology
Talk Title:
Measurement of currents and fields of CDM discharges with > 20 GHz bandwidth
Abstract:
With heterogenous integration the interest in CDM discharges below 100V is growing. The low voltages and small chiplets lead to rise times below 15ps. To capture these rise times new antennas and current sensors are needed. The talk will present an antenna that operates from 0.4-60+ GHz and a new current target with > 25 GHz bandwidth. The capture devices and captured CDM data will be presented.
Bio:
David Pommerenke is professor at Graz University of Technology in the Electronics Institute. He joined TU Graz in 2020 after being professor for 19 years at the EMC group of Missouri Science and Technology. His interest is EMC, electronics, antennas and test and measurements.
Dr. Milind Furia
Micron Technology, USA
Talk Title:
Need for reducing ESD targets for Memory Components
Abstract:
Bio:
Mr. Leonardo Di Biccari
STMicroelectronics, Italy
Talk Title:
Charge trapping mechanism in thick oxide of HV LDMOS under CDM events
Abstract:
Oxide charge trapping is deeply investigated phenomenon for IC reliability, considering different scenario than nanosecond time domain. In this work the charge trapping mechanism in HV LDMOS thick oxide under nanosecond event is investigated, by means of characterizations and TCAD simulations. Impact of different CDM test methods and procedures is discussed. This work provides meaningful results for the reliability of the HV ICs, highlighting the impact of the charge trapping phenomenon on HV devices’ physics in case of fast events, and introduces the potential consequences in terms of the IC ESD testing.
Bio:
Leonardo Di Biccari graduated (summa cum laude) in electronic engineering at the University of Padova. He is Senior member of the Technical Staff at STMicroelectronics, leading the ESD protections development group for BCD technologies. Leonardo represents STMicroelectronics in the ESDA working groups (co-chair of the TLP WG), and he serves on the ESDA Standard Committee. Leonardo authored several papers presented at ESREF, IRPS and EOS/ESD Symposium, where he regularly serves on the Technical Program Committee.
Dr. Dolphin Abessolo Bidzo
NXP Semiconductors, Netherlands
Talk Title:
ESD Robustness Challenges for RF and High-Speed I/O Applications
Abstract:
The continued aggressive scaling of high-speed and RF I/O bandwidth is critical for the industry. However, achieving higher bandwidth with increasing data rates, while maintaining acceptable power consumption, area efficiency, and reliability, presents significant design challenges. This is due to the very limited ESD protection capacitance load “budget” of those pins for functional reasons. Thus, the ESD protection capability of ultra-high-speed and RF I/Os is impacted. Furthermore, with the gate oxide breakdown voltage trending downwards with each new advanced CMOS technology node, devices are more vulnerable to ESD strikes. This presentation will give an overview of RF ESD design techniques and trade-offs and will show the required transient CDM simulation of RF I/O’s. The CDM level for ultra-High-Speed I/O interfaces will also be discussed.
Bio:
Dr. Ing. Dolphin ABESSOLO BIDZO earned two Masters of Science degrees in Telecommunications & Multimedia Engineering and Electronics in 2004, followed by a Ph.D. in Electronics & Microelectronics in 2007 from leading French institutions (ENSICAEN, University of Rouen and University of Caen). Dolphin has more than 20 years of experience at NXP Semiconductors as a Senior Principal RF, High-Speed ESD & Latch-Up Design Engineer. He was awarded the prestigious NXP Notable Inventor title.
