Dr. Harald Josef Erhard Gossner

Intel Corporation, Germany

Talk Title:
ESD Protection Challenges for AI Compute Applications

Abstract:
Challenges in ESD protection development have bifurcated into high voltage components and complex, high speed multi die systems using digital leading edge technologies like Gate all around (GAA). Hardware advancements in AI applications rely on heterogenous integration system of chips in downscaled technologies with millions of die-to die interfaces. The roadmap of these technologies is set in context with the available ESD solutions and the need of new developments. The challenges are connected to ESD design concepts, pre-silicon validation and testing. The presentation touches on all of them and indicates the steps to be taken for an ESD protection embedded into these future IC solutions.

Bio:
Dr. Harald Gossner is Senior Principal Engineer at Intel and IEEE Fellow. He has authored and co-authored 150 technical papers and two books in the fields of ESD and device physics, where he also holds 120 patents. He is the recipient of the outstanding achievement award of EOS/ESD Association as highest award for his contributions to the field of ESD. He is the cofounder and co-chair of the Industry Council on ESD Target Levels.

Dr. Charvaka Duvvury

iT2 Technologies

Talk Title:
Five Decades of ESD Technology Development: Breakthrough Events and Milestones

Abstract:
Since the first awareness of its pervasive nature in the electronic industry, beginning during the late 70s ESD development progressed through a series of pioneering papers, which included device physics, the nature of crucial static discharge events, and the evolution of protection concepts driven by the explosion of different IC technologies and circuit design applications. This address will take the audience from the very beginning, highlighting all the key developments from several pioneering researchers. The talk will include the timeline for ESD understanding, ESD testing, ESD control, and ESD protection. Finally, the talk will give a glimpse of what could be important for the next few decades.

Bio:
Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Dr. Wolfgang Stadler

Gärtner & Stadler ESD Consulting, Germany

Talk Title:
ESD Control for Chip Designers & Test Engineers

Abstract:
ESD control measures, as defined in ESD control standards such as ANSI/ESD S20.20 or IEC 61340-5-1, are crucial for preventing ESD damage to ESD-sensitive items. These ESD control standards require a minimum ESD robustness of 100 V according to HBM and 200 V for CDM for ICs to ensure safe handling. However, the waveforms of actual ESD events in the process do not always match the qualification waveforms, and therefore, passing an ESD qualification does not necessarily guarantee that all handling issues will be avoided. The situation is even more concerning for system-level ESD, such as charged board or cable discharge events, where there is no widely accepted characterization method, and limits in the ESD control standards do not exist.

We will discuss the (mis)correlation between IC ESD qualification waveforms and actual risks in handling ICs, boards, and systems, as well as which ESD characterization methods can be used for ESD process assessment.

Bio:
Wolfgang Stadler is a consultant for electrostatic discharge (ESD) and electrical overstress (EOS) with 30 years of experience in both areas; he is co-founder and co-owner of Gärtner & Stadler ESD Consulting GmbH & Co. KG.

Wolfgang Stadler received his diploma in physics in 1991 and his PhD degree from the Physics Department at the Technical University of Munich in 1995. In 1995, he joined Siemens’ semiconductor division, which became Infineon Technologies in 1999. His focus was on developing ESD-protection concepts in CMOS technologies and innovative ESD topics. In this role, he coordinated several European and German ESD funding projects. Since 2003, he has also been responsible for the measurement of I/O cells and PHYs. In 2011, he joined Intel. Within Intel’s Corporate Quality Network, he was responsible for the ESD Control Program and ESD risk assessment and supported ESD device testing and qualification.

Wolfgang holds several patents related to ESD. He is the author or co-author of more than 120 technical papers and has co-authored a book on ESD simulation. He teaches regular courses on ESD device testing, ESD qualification, ESD control measures (such as ESD Technician Certification), and ESD process assessment. He actively participates in the EOS/ESD Association and IEC working groups focused on ESD control and process assessment. Wolfgang is co-chairing the ESDA business unit “Standardization” and currently chairing the EOS/ESD Association Working Groups “Transient Latch-up”, “Manufacturing Task Team”, and “Seating”; since 2013, he has been co-chairing the ESDA Working Group 17 “Process Assessment”. Wolfgang has been elected to serve on the Board of Directors of the EOS/ESD Association for 2014–2019 and is now appointed as a director. Since 2015, he has served as president of the German ESD FORUM e.V. In 2019, he received the Outstanding Contribution Award from the EOS/ESD Association.

Dr. Efraim Aharoni

Tower Semiconductor, Israel

Talk Title:
Foundry ESD deliverables and characterization for ESD

Abstract:
Foundries manufacturing integrated circuits should supply a variety of ESD-related deliverables in their Process Design Kit (PDK). The trade-off between the ESD capability and the signal integrity is reflected in key ESD parameters extracted from dedicated measurements. An effective ESD protection, planned during design level, requires dedicated tools and data exchange. This talk highlights the recommended guidance to the ESD engineer in the foundry, creating and supplying the ESD portion of the PDK and other deliverables. In particular, providing special parameters required for design of an optimized ESD protection in the IC. ESDA Working Group 22 on ‘ESD Parameters’ technical reports; ‘Relevant ESD foundry parameters for seamless ESD design and verification flow’ and ‘ESD parameters from Intellectual Property (IP) providers’, will be highlighted.

Bio:
Efraim Aharoni received the B.Sc./Ph.D. in Physics in 1989/1994, from the Technion, Israel. In 1993 he joined Tower Semiconductor and is leading the ESD/LU fields. This involves the development of ESD devices and protection, characterization, design guidelines, PDK, PERC, and customer support. He is also lecturing in the EE department in the Academic Kinneret College. Efraim was a member of the IEW and EOS/ESD Technical Program Committees. He is a co-chair of WG22 (ESD parameters).

Mr. Vinayakam Subramanian
Director, Application Engineering

Ansys, India

Talk Title:
2.5D/3D-IC ESD Reliability Analysis

Abstract:
2.5D/3D-IC have unique ESD challenges due to different IOs, die-to-die links, technologies, suppliers, and design methods that are different from SoC. Managing new ESD risks from die-to-die links considering the effect of different technologies. Handling differences from multiple suppliers of 3D-IC chip structures while adapting different ESD design methods. 3D-IC designers need a systematic and automated way to verify ESD protection on all the chips in 3D-IC to perform ESD analysis all together to overcome all these challenges. Most importantly, to analyze all the chips concurrently, designers need scalable platform to efficiently handle such a large complex designs. This talk provides more details and insight on multi-die ESD analysis to ensure ESD reliability of 3D-IC.

Bio:
Mr Vinayakam Subramanian is a subject matter expert in Power Integrity, Signal Integrity and ESD/Reliability simulations on advanced IC designs with over 18years of experience in this space. He loves to solve multi-physics challenges that require combining technologies across various domains. He joined Ansys in 2006, has taken several diverse roles across field application engineering & product management and is currently working as Director of Application Engineering, based out of India.

Prof. Nathan Jack
Department Chair, Computer Science and Engineering

Brigham Young University Idaho, USA

Talk Title:
Latchup in Contemporary and Emerging CMOS Technologies

Abstract:
Latchup remains a critical reliability concern in 7 nm FinFET technologies and beyond. Despite earlier predictions that lower power supply voltages—particularly those near or below 1 V—would eliminate latchup, recent evidence shows that this threat persists. This talk will begin with a concise overview of latchup mechanisms, including single-event latchup (SEL). It will then review key studies from the past 3–5 years addressing latchup risks and mitigation strategies in leading-edge technologies. Finally, the presentation will explore emerging trends such as buried power rails and backside power delivery, with a focus on their implications for SEL susceptibility in future nodes.

Bio:
Nathan Jack is the chair of the Computer Science and Engineering Department at Brigham Young University Idaho. Previously, Dr. Jack worked at Intel Corp. for 10 years in the ESD and latchup research and development group. Dr. Jack also served for three years on the board of directors for the Electrostatic Discharge Association.Dr. Jack is the recipient of several research awards, best paper awards, has published over 25 papers, and holds several patents.

Mr. Matthew Hogan
Director of Product Management

Siemens EDA, USA

Talk Title:
Improving the fidelity of ESD margins with context-aware ESD simulation

Abstract:
Conservative design rules and constraints are often used in reliability verification flows. By combining the leading solutions for ESD reliability verification and SPICE simulation technologies, SPICE-accurate full-chip simulation becomes possible in a compelling flow for design teams looking to better understand their ESD design margins.

We will explore the challenges of traditional parasitic extraction methods, sourcing appropriate SPICE simulation models and demonstrate how a context-aware ESD simulation flow can improve the fidelity of results to better understand ESD design margins, while performing full-chip SPICE-accurate simulations on ESD paths within your design.

Bio:
Matthew Hogan is a Product Management Director for Calibre Design Solutions at Siemens Digital Industries Software, with over two decades of design, field and product development experience, working actively with customers on IC reliability verification topics. An active IEEE volunteer, he has been the past general chair for both the IEW and IIRW, and has previously been on the Board of Directors for the ESD Association. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew.hogan@siemens.com.

Dr. Krzysztof Domanski

Intel Germany

Talk Title:
ESD codesign in leading-edge Ribbon-FET technologies

Abstract:
The ESD codesign in leading-edge Ribbon-FET or Gate All Around FET (GAA-FET) technologies pose new challenges and opportunities. On the one hand, the ESD design window shrinks permanently with new technology generations with reducing feature-size and victim-breakdown voltages. The Ribbon-FET technology might not offer features traditionally used for ESD codesign like, thyristors, special ESD implantation, drain extensions, or IO devices. A further constraint for ESD design window results from ESD-diodes themselves, because of reduced reverse-breakdown in a dual- diode protection scheme. On the other hand, there are new opportunities arising from Ribbon-FET specific design rules or technology features, that can be turned into advantage for ESD. In this presentation the new trends and techniques for ESD-codesign in Ribbon-FET/GAA-FET will be outlined.

Bio:
Krzysztof Domanski has started his career in 2003 at Infineon Technologies as a Ph.D. student in the field of Transient Latchup. In 2005 he received his Ph.D. degree in physics at the Nicolaus Copernicus University, in Torun, Poland. Since 2004 he joined the ESD/LU team at the Infineon Technologies where he has developed ESD/Latchup protection concepts. In 2013 he joined Intel, where he now works as a Principal Engineer in the field of ESD/Latchup on chip and system level. He is an author or co-author of more than 30 technical papers, over 30 patents and several ESDA technical reports.

Dr. Steffen Holland
Technical Director

Nexperia Germany GmbH

Talk Title:
System level ESD protection for high-speed data lines

Abstract:
ICs with advanced CMOS technology are often used for high-speed data lines. With shrinking structure sizes these ICs become more sensitive to overvoltage during an ESD event. The usage of TVS protection devices enable a high system level ESD protection level but special care must be taken to keep the transient voltage at the IC at an acceptably low level. The presentation will give an overview of the origin of overshoot voltage in TVS protection devices. Device and PCB layout parameters and their effect on the peak voltage at the IC will be shown for a USB-C SuperSpeed data line application.

Bio:
Steffen Holland received his PhD in Physics from the University of Hamburg. He joined Nexperia in the bipolar process development group Hamburg, Germany in 2005. The focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He works now TVS protection devices. His interests are system level ESD simulations, and he is chair of the ESDA working group 26. He serves in the Board of Directors at the ESDA.

Prof. Carlo De Santi
Associate Professor

University of Padova. Italy

Talk Title:
TLP effects on normally-off p-GaN gate power HEMTs with Schottky gate

Abstract:
In this work, we will present the effect of transmission line pulse tests on normally-off p-GaN gate power HEMTs with Schottky gate metal. The effect of the line charging voltage on both static and dynamic performance will be investigated, as well as the role of the gate bias in the degradation. Deep level characterization techniques will be used to identify the root cause of the degradation and failure processes.

Bio:
Carlo De Santi is an associate professor at the University of Padova. His research activities are characterization, modeling of physical processes and reliability of electronic and optoelectronic devices for power electronics and radio frequency systems, LEDs and lasers in the UV, visible monochromatic and white spectral range, devices for silicon photonics, solar cells and photodetectors, phosphors and systems for lighting applications. He co-authored more than 450 papers, including 60 invited ones.

Dr. Akram A Salman
VP/Master Samsung Fondary (ESD team leader)

Samsung Electronics , South Korea

Talk Title:
State-of-the-art advances in ESD design and testing for Digital and Analog technologies

Abstract:
As the size of digital and analog technologies continues to decrease with each node with added complexity, the challenges associated with developing optimized minimum size ESD solutions have intensified. This is primarily due to the reduction of the ESD design window, the increase in die size, the heightened sensitivity of devices, and the necessity for on-chip system-level ESD protection. In this research, we will delve into the advancements in ESD device and circuit design for state-of-the-art digital technologies, such as FinFET and GAA, as well as analog and HV technologies. Furthermore, we will explore the enhancement of ESD testing methods, including Multi-reflection TLP (MRTLP), to characterize and design more optimal ESD solutions for chip-level and system-level protection. Additionally, we will assess the reverse recovery effects on SOA for high-power devices.

Bio:
Dr. Salman, a 2002 PhD recipient from George Mason University, has over 23 years of experience in ESD at IBM, AMD, TI, and Apple. Currently, he leads the ESD team at Samsung Electronics, responsible for developing digital and analog technologies. His ESD device/circuit design and development have earned him recognition, including Best Paper Awards in EOS/ESD symposium and Int IEEE SOI Conference. He holds over 75 US patents, has published over 100 papers in international conferences and journals, and has received over 1000 citations. Dr. Salman has also served as a panelist and session chair at EOS/ESD symposium and has invited talks at IEEE S3S conference.

Dr. Ann Concannon
DMTS

Texas Instruments

Talk Title:
Navigating ESD protection challenges in Analog design

Abstract:
As the analog semiconductor market continues to expand into diverse applications—ranging from automotive and industrial power management to high-performance RF and sensor interfaces—the challenges of Electrostatic Discharge (ESD) protection become increasingly complex. Unlike digital circuits, where standardized ESD design strategies are well established, analog and mixed-signal ICs demand tailored solutions due to their unique performance constraints, high voltage operation, and sensitivity to parasitic effects. The author will reflect on the key ESD protection options in analog semiconductor design and possible tradeoffs to meet the challenges these present.

Bio:
Ann Concannon is a recognized leader in semiconductor technology, with a distinguished career spanning academia, research, and industry. She earned her BE in 1991 and Ph.D. in 1996 from the National University of Ireland and led a research group at the Tyndall Research Center from 1996 to 2000 before transitioning to industry, joining National Semiconductor and Texas Instruments in 2011. She is a technical leader in the ESD team within the Advanced Technology Development Group

Dr. Karuna Nidhi
Manager of ESD-LU and SOA Department

Tata Semiconductor Manufacturing Pvt. Ltd. (TSMPL), Taiwan

Talk Title:
ESD Design flow and Major concern for ICs

Abstract:
ESD check flow is an important part of design verification for any integrated circuit (IC) or chip design. To provide sufficient protection against ESD events, IC designers and ESD engineers must make sure that start from the selection of suitable ESD protection devices, its implementation and EDA check must move smoothly to successful Tape-out of the designed product. In this talk, presenter will talk about ESD check flow for IC product design at different phases throughout the product design that will cover together with schematic-based, layout-based flow check along with measurement flow. This approach allows for the avoidance of ESD related design and measurement flaws, reducing the overall design cycle time. Presenter will also highlight on some major concerns during this check flow.

Bio:
Dr. Karuna Nidhi received his Masters and PhD degree from Taiwan. He joined Vanguard International Semiconductor Corp., Hsinchu in 2011-12 and worked over 9 years with Technology development Department. He was responsible for Power devices and ESD Engineering. He is currently leading ESD and Power Device team with Tata Semiconductor Manufacturing Pvt. Ltd (TSMPL) and based in Taiwan. Prior to TSMPL, he was Technical Manager with Richtek Technology corporation, Zhupei, Hsinchu, Taiwan.He is Senior member of IEEE, has authored or coauthored over 30 prestigious journal articles/conference papers and granted more than 15 USA/Taiwan patents. His current research interests include device engineering, ESD protection design and Reliability.

Dr. Slavica Malobabic
ESD Engineer

Cirrus Logic, Austin, USA

Talk Title:
Parasitic PNPs and NPNs in ESD and latch up over different time domains

Abstract:
This tutorial summarizes parasitic NPNs, PNPs, and their interactions within the nano second to milli second time domain. We first go through the basics of Electrostatic Discharge (ESD) and Latch Up (LU). Then we illustrate parasitic NPNs and PNPs during ESD or other transient type events, followed by LU. We will point out issues to watch out for and test structures to mitigate the parasitic NPNs and PNPs for a variety of use cases.

Bio:
Slavica Malobabic received her PhD in Electrical Engineering from the University of Central Florida, Orlando in 2011 for her work on Transient Safe Operating Area (TSOA) for ESD applications. From 2011, she was part of the Technology Development Group at Maxim Integrated Products (now Analog Devices) in San Jose, CA on new technology ground up ESD development, ESD and LU design rules, product reviews and troubleshooting. Since 2021 she is part of the IP and ESD Technology Engineering R&D team in Cirrus Logic, Austin, TX where she focuses on ESD and LU development on different foundry processes.

Dr. Ping-Hsun, Su
VP CMOS Technology

Tata Semiconductor Manufacturing Pvt. Ltd (TSMPL), Taiwan

Talk Title:
ESD Challenges from Process transfer into different Fabs

Abstract:
As the technology continues to scaling down, the process variation to impact on device and ESD is getting more important. The aggressively scaled feature size leads to serious characteristic degradation and fluctuation of devices. Expect known process variation and randomness effects, there are still many unknown sources of variation that govern uncertainty of devices and ESD circuits. There are more unknown ESD Challenges from process transfer into different Fabs. The author will reflect on the key ESD protection options in semiconductor process , device , and design and possible tradeoffs to meet the challenges these present.

Bio:
Dr. Su received his PhD in Communications Engineering from the University of National Yang Ming Chiao Tung. He has over 25 years’ semiconductor experience at TSMC, Samsung, Tata in the field of R&D including Bulk, SOI, memory, and ESD technology. He holds over 80 patents and has authored or coauthored over 15 prestigious journal articles and conference papers His current research interests include device engineering and circuit design for process health monitor, SPICE model generation, and ESD protection.